STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_dma.c 00004 * @author MCD Application Team 00005 * @brief DMA LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 #if defined(USE_FULL_LL_DRIVER) 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx_ll_dma.h" 00039 #include "stm32f4xx_ll_bus.h" 00040 #ifdef USE_FULL_ASSERT 00041 #include "stm32_assert.h" 00042 #else 00043 #define assert_param(expr) ((void)0U) 00044 #endif 00045 00046 /** @addtogroup STM32F4xx_LL_Driver 00047 * @{ 00048 */ 00049 00050 #if defined (DMA1) || defined (DMA2) 00051 00052 /** @defgroup DMA_LL DMA 00053 * @{ 00054 */ 00055 00056 /* Private types -------------------------------------------------------------*/ 00057 /* Private variables ---------------------------------------------------------*/ 00058 /* Private constants ---------------------------------------------------------*/ 00059 /* Private macros ------------------------------------------------------------*/ 00060 /** @addtogroup DMA_LL_Private_Macros 00061 * @{ 00062 */ 00063 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ 00064 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ 00065 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) 00066 00067 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ 00068 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ 00069 ((__VALUE__) == LL_DMA_MODE_PFCTRL)) 00070 00071 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ 00072 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) 00073 00074 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ 00075 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) 00076 00077 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ 00078 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ 00079 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) 00080 00081 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ 00082 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ 00083 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) 00084 00085 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) 00086 00087 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ 00088 ((__VALUE__) == LL_DMA_CHANNEL_1) || \ 00089 ((__VALUE__) == LL_DMA_CHANNEL_2) || \ 00090 ((__VALUE__) == LL_DMA_CHANNEL_3) || \ 00091 ((__VALUE__) == LL_DMA_CHANNEL_4) || \ 00092 ((__VALUE__) == LL_DMA_CHANNEL_5) || \ 00093 ((__VALUE__) == LL_DMA_CHANNEL_6) || \ 00094 ((__VALUE__) == LL_DMA_CHANNEL_7)) 00095 00096 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ 00097 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ 00098 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ 00099 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) 00100 00101 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ 00102 (((STREAM) == LL_DMA_STREAM_0) || \ 00103 ((STREAM) == LL_DMA_STREAM_1) || \ 00104 ((STREAM) == LL_DMA_STREAM_2) || \ 00105 ((STREAM) == LL_DMA_STREAM_3) || \ 00106 ((STREAM) == LL_DMA_STREAM_4) || \ 00107 ((STREAM) == LL_DMA_STREAM_5) || \ 00108 ((STREAM) == LL_DMA_STREAM_6) || \ 00109 ((STREAM) == LL_DMA_STREAM_7) || \ 00110 ((STREAM) == LL_DMA_STREAM_ALL))) ||\ 00111 (((INSTANCE) == DMA2) && \ 00112 (((STREAM) == LL_DMA_STREAM_0) || \ 00113 ((STREAM) == LL_DMA_STREAM_1) || \ 00114 ((STREAM) == LL_DMA_STREAM_2) || \ 00115 ((STREAM) == LL_DMA_STREAM_3) || \ 00116 ((STREAM) == LL_DMA_STREAM_4) || \ 00117 ((STREAM) == LL_DMA_STREAM_5) || \ 00118 ((STREAM) == LL_DMA_STREAM_6) || \ 00119 ((STREAM) == LL_DMA_STREAM_7) || \ 00120 ((STREAM) == LL_DMA_STREAM_ALL)))) 00121 00122 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ 00123 ((STATE) == LL_DMA_FIFOMODE_ENABLE)) 00124 00125 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ 00126 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ 00127 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ 00128 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) 00129 00130 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ 00131 ((BURST) == LL_DMA_MBURST_INC4) || \ 00132 ((BURST) == LL_DMA_MBURST_INC8) || \ 00133 ((BURST) == LL_DMA_MBURST_INC16)) 00134 00135 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ 00136 ((BURST) == LL_DMA_PBURST_INC4) || \ 00137 ((BURST) == LL_DMA_PBURST_INC8) || \ 00138 ((BURST) == LL_DMA_PBURST_INC16)) 00139 00140 /** 00141 * @} 00142 */ 00143 00144 /* Private function prototypes -----------------------------------------------*/ 00145 00146 /* Exported functions --------------------------------------------------------*/ 00147 /** @addtogroup DMA_LL_Exported_Functions 00148 * @{ 00149 */ 00150 00151 /** @addtogroup DMA_LL_EF_Init 00152 * @{ 00153 */ 00154 00155 /** 00156 * @brief De-initialize the DMA registers to their default reset values. 00157 * @param DMAx DMAx Instance 00158 * @param Stream This parameter can be one of the following values: 00159 * @arg @ref LL_DMA_STREAM_0 00160 * @arg @ref LL_DMA_STREAM_1 00161 * @arg @ref LL_DMA_STREAM_2 00162 * @arg @ref LL_DMA_STREAM_3 00163 * @arg @ref LL_DMA_STREAM_4 00164 * @arg @ref LL_DMA_STREAM_5 00165 * @arg @ref LL_DMA_STREAM_6 00166 * @arg @ref LL_DMA_STREAM_7 00167 * @arg @ref LL_DMA_STREAM_ALL 00168 * @retval An ErrorStatus enumeration value: 00169 * - SUCCESS: DMA registers are de-initialized 00170 * - ERROR: DMA registers are not de-initialized 00171 */ 00172 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) 00173 { 00174 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; 00175 ErrorStatus status = SUCCESS; 00176 00177 /* Check the DMA Instance DMAx and Stream parameters*/ 00178 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); 00179 00180 if (Stream == LL_DMA_STREAM_ALL) 00181 { 00182 if (DMAx == DMA1) 00183 { 00184 /* Force reset of DMA clock */ 00185 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); 00186 00187 /* Release reset of DMA clock */ 00188 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); 00189 } 00190 else if (DMAx == DMA2) 00191 { 00192 /* Force reset of DMA clock */ 00193 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); 00194 00195 /* Release reset of DMA clock */ 00196 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); 00197 } 00198 else 00199 { 00200 status = ERROR; 00201 } 00202 } 00203 else 00204 { 00205 /* Disable the selected Stream */ 00206 LL_DMA_DisableStream(DMAx,Stream); 00207 00208 /* Get the DMA Stream Instance */ 00209 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); 00210 00211 /* Reset DMAx_Streamy configuration register */ 00212 LL_DMA_WriteReg(tmp, CR, 0U); 00213 00214 /* Reset DMAx_Streamy remaining bytes register */ 00215 LL_DMA_WriteReg(tmp, NDTR, 0U); 00216 00217 /* Reset DMAx_Streamy peripheral address register */ 00218 LL_DMA_WriteReg(tmp, PAR, 0U); 00219 00220 /* Reset DMAx_Streamy memory address register */ 00221 LL_DMA_WriteReg(tmp, M0AR, 0U); 00222 00223 /* Reset DMAx_Streamy memory address register */ 00224 LL_DMA_WriteReg(tmp, M1AR, 0U); 00225 00226 /* Reset DMAx_Streamy FIFO control register */ 00227 LL_DMA_WriteReg(tmp, FCR, 0x00000021U); 00228 00229 /* Reset Channel register field for DMAx Stream*/ 00230 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0); 00231 00232 if(Stream == LL_DMA_STREAM_0) 00233 { 00234 /* Reset the Stream0 pending flags */ 00235 DMAx->LIFCR = 0x0000003FU; 00236 } 00237 else if(Stream == LL_DMA_STREAM_1) 00238 { 00239 /* Reset the Stream1 pending flags */ 00240 DMAx->LIFCR = 0x00000F40U; 00241 } 00242 else if(Stream == LL_DMA_STREAM_2) 00243 { 00244 /* Reset the Stream2 pending flags */ 00245 DMAx->LIFCR = 0x003F0000U; 00246 } 00247 else if(Stream == LL_DMA_STREAM_3) 00248 { 00249 /* Reset the Stream3 pending flags */ 00250 DMAx->LIFCR = 0x0F400000U; 00251 } 00252 else if(Stream == LL_DMA_STREAM_4) 00253 { 00254 /* Reset the Stream4 pending flags */ 00255 DMAx->HIFCR = 0x0000003FU; 00256 } 00257 else if(Stream == LL_DMA_STREAM_5) 00258 { 00259 /* Reset the Stream5 pending flags */ 00260 DMAx->HIFCR = 0x00000F40U; 00261 } 00262 else if(Stream == LL_DMA_STREAM_6) 00263 { 00264 /* Reset the Stream6 pending flags */ 00265 DMAx->HIFCR = 0x003F0000U; 00266 } 00267 else if(Stream == LL_DMA_STREAM_7) 00268 { 00269 /* Reset the Stream7 pending flags */ 00270 DMAx->HIFCR = 0x0F400000U; 00271 } 00272 else 00273 { 00274 status = ERROR; 00275 } 00276 } 00277 00278 return status; 00279 } 00280 00281 /** 00282 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. 00283 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : 00284 * @arg @ref __LL_DMA_GET_INSTANCE 00285 * @arg @ref __LL_DMA_GET_STREAM 00286 * @param DMAx DMAx Instance 00287 * @param Stream This parameter can be one of the following values: 00288 * @arg @ref LL_DMA_STREAM_0 00289 * @arg @ref LL_DMA_STREAM_1 00290 * @arg @ref LL_DMA_STREAM_2 00291 * @arg @ref LL_DMA_STREAM_3 00292 * @arg @ref LL_DMA_STREAM_4 00293 * @arg @ref LL_DMA_STREAM_5 00294 * @arg @ref LL_DMA_STREAM_6 00295 * @arg @ref LL_DMA_STREAM_7 00296 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. 00297 * @retval An ErrorStatus enumeration value: 00298 * - SUCCESS: DMA registers are initialized 00299 * - ERROR: Not applicable 00300 */ 00301 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) 00302 { 00303 /* Check the DMA Instance DMAx and Stream parameters*/ 00304 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); 00305 00306 /* Check the DMA parameters from DMA_InitStruct */ 00307 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); 00308 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); 00309 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); 00310 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); 00311 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); 00312 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); 00313 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); 00314 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel)); 00315 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); 00316 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); 00317 /* Check the memory burst, peripheral burst and FIFO threshold parameters only 00318 when FIFO mode is enabled */ 00319 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) 00320 { 00321 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); 00322 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); 00323 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); 00324 } 00325 00326 /*---------------------------- DMAx SxCR Configuration ------------------------ 00327 * Configure DMAx_Streamy: data transfer direction, data transfer mode, 00328 * peripheral and memory increment mode, 00329 * data size alignment and priority level with parameters : 00330 * - Direction: DMA_SxCR_DIR[1:0] bits 00331 * - Mode: DMA_SxCR_CIRC bit 00332 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit 00333 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit 00334 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits 00335 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits 00336 * - Priority: DMA_SxCR_PL[1:0] bits 00337 */ 00338 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ 00339 DMA_InitStruct->Mode | \ 00340 DMA_InitStruct->PeriphOrM2MSrcIncMode | \ 00341 DMA_InitStruct->MemoryOrM2MDstIncMode | \ 00342 DMA_InitStruct->PeriphOrM2MSrcDataSize | \ 00343 DMA_InitStruct->MemoryOrM2MDstDataSize | \ 00344 DMA_InitStruct->Priority 00345 ); 00346 00347 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) 00348 { 00349 /*---------------------------- DMAx SxFCR Configuration ------------------------ 00350 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : 00351 * - FIFOMode: DMA_SxFCR_DMDIS bit 00352 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits 00353 */ 00354 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); 00355 00356 /*---------------------------- DMAx SxCR Configuration -------------------------- 00357 * Configure DMAx_Streamy: memory burst transfer with parameters : 00358 * - MemBurst: DMA_SxCR_MBURST[1:0] bits 00359 */ 00360 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); 00361 00362 /*---------------------------- DMAx SxCR Configuration -------------------------- 00363 * Configure DMAx_Streamy: peripheral burst transfer with parameters : 00364 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits 00365 */ 00366 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst); 00367 } 00368 00369 /*-------------------------- DMAx SxM0AR Configuration -------------------------- 00370 * Configure the memory or destination base address with parameter : 00371 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits 00372 */ 00373 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); 00374 00375 /*-------------------------- DMAx SxPAR Configuration --------------------------- 00376 * Configure the peripheral or source base address with parameter : 00377 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits 00378 */ 00379 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); 00380 00381 /*--------------------------- DMAx SxNDTR Configuration ------------------------- 00382 * Configure the peripheral base address with parameter : 00383 * - NbData: DMA_SxNDT[15:0] bits 00384 */ 00385 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); 00386 00387 /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- 00388 * Configure the peripheral base address with parameter : 00389 * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits 00390 */ 00391 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel); 00392 00393 return SUCCESS; 00394 } 00395 00396 /** 00397 * @brief Set each @ref LL_DMA_InitTypeDef field to default value. 00398 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. 00399 * @retval None 00400 */ 00401 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) 00402 { 00403 /* Set DMA_InitStruct fields to default values */ 00404 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; 00405 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; 00406 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; 00407 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; 00408 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; 00409 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; 00410 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; 00411 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; 00412 DMA_InitStruct->NbData = 0x00000000U; 00413 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0; 00414 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; 00415 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; 00416 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; 00417 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; 00418 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; 00419 } 00420 00421 /** 00422 * @} 00423 */ 00424 00425 /** 00426 * @} 00427 */ 00428 00429 /** 00430 * @} 00431 */ 00432 00433 #endif /* DMA1 || DMA2 */ 00434 00435 /** 00436 * @} 00437 */ 00438 00439 #endif /* USE_FULL_LL_DRIVER */ 00440 00441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/