STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX LL module. 00006 @verbatim 00007 ============================================================================== 00008 ##### How to use this driver ##### 00009 ============================================================================== 00010 [..] 00011 The LL CORTEX driver contains a set of generic APIs that can be 00012 used by user: 00013 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick 00014 functions 00015 (+) Low power mode configuration (SCB register of Cortex-MCU) 00016 (+) MPU API to configure and enable regions 00017 (MPU services provided only on some devices) 00018 (+) API to access to MCU info (CPUID register) 00019 (+) API to enable fault handler (SHCSR accesses) 00020 00021 @endverbatim 00022 ****************************************************************************** 00023 * @attention 00024 * 00025 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00026 * 00027 * Redistribution and use in source and binary forms, with or without modification, 00028 * are permitted provided that the following conditions are met: 00029 * 1. Redistributions of source code must retain the above copyright notice, 00030 * this list of conditions and the following disclaimer. 00031 * 2. Redistributions in binary form must reproduce the above copyright notice, 00032 * this list of conditions and the following disclaimer in the documentation 00033 * and/or other materials provided with the distribution. 00034 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00035 * may be used to endorse or promote products derived from this software 00036 * without specific prior written permission. 00037 * 00038 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00039 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00040 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00041 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00042 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00043 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00044 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00045 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00046 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00047 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00048 * 00049 ****************************************************************************** 00050 */ 00051 00052 /* Define to prevent recursive inclusion -------------------------------------*/ 00053 #ifndef __STM32F4xx_LL_CORTEX_H 00054 #define __STM32F4xx_LL_CORTEX_H 00055 00056 #ifdef __cplusplus 00057 extern "C" { 00058 #endif 00059 00060 /* Includes ------------------------------------------------------------------*/ 00061 #include "stm32f4xx.h" 00062 00063 /** @addtogroup STM32F4xx_LL_Driver 00064 * @{ 00065 */ 00066 00067 /** @defgroup CORTEX_LL CORTEX 00068 * @{ 00069 */ 00070 00071 /* Private types -------------------------------------------------------------*/ 00072 /* Private variables ---------------------------------------------------------*/ 00073 00074 /* Private constants ---------------------------------------------------------*/ 00075 00076 /* Private macros ------------------------------------------------------------*/ 00077 00078 /* Exported types ------------------------------------------------------------*/ 00079 /* Exported constants --------------------------------------------------------*/ 00080 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants 00081 * @{ 00082 */ 00083 00084 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source 00085 * @{ 00086 */ 00087 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ 00088 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ 00089 /** 00090 * @} 00091 */ 00092 00093 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type 00094 * @{ 00095 */ 00096 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ 00097 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ 00098 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ 00099 /** 00100 * @} 00101 */ 00102 00103 #if __MPU_PRESENT 00104 00105 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control 00106 * @{ 00107 */ 00108 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ 00109 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ 00110 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ 00111 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ 00112 /** 00113 * @} 00114 */ 00115 00116 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number 00117 * @{ 00118 */ 00119 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ 00120 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ 00121 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ 00122 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ 00123 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ 00124 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ 00125 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ 00126 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ 00127 /** 00128 * @} 00129 */ 00130 00131 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size 00132 * @{ 00133 */ 00134 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ 00135 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ 00136 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ 00137 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ 00138 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ 00139 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ 00140 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ 00141 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ 00142 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ 00143 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ 00144 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ 00145 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ 00146 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ 00147 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ 00148 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ 00149 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ 00150 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ 00151 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ 00152 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ 00153 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ 00154 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ 00155 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ 00156 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ 00157 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ 00158 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ 00159 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ 00160 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ 00161 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ 00162 /** 00163 * @} 00164 */ 00165 00166 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges 00167 * @{ 00168 */ 00169 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ 00170 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ 00171 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ 00172 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ 00173 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ 00174 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ 00175 /** 00176 * @} 00177 */ 00178 00179 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level 00180 * @{ 00181 */ 00182 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ 00183 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ 00184 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ 00185 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ 00186 /** 00187 * @} 00188 */ 00189 00190 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access 00191 * @{ 00192 */ 00193 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ 00194 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ 00195 /** 00196 * @} 00197 */ 00198 00199 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access 00200 * @{ 00201 */ 00202 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ 00203 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ 00204 /** 00205 * @} 00206 */ 00207 00208 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access 00209 * @{ 00210 */ 00211 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ 00212 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access 00218 * @{ 00219 */ 00220 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ 00221 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ 00222 /** 00223 * @} 00224 */ 00225 #endif /* __MPU_PRESENT */ 00226 /** 00227 * @} 00228 */ 00229 00230 /* Exported macro ------------------------------------------------------------*/ 00231 00232 /* Exported functions --------------------------------------------------------*/ 00233 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions 00234 * @{ 00235 */ 00236 00237 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK 00238 * @{ 00239 */ 00240 00241 /** 00242 * @brief This function checks if the Systick counter flag is active or not. 00243 * @note It can be used in timeout function on application side. 00244 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag 00245 * @retval State of bit (1 or 0). 00246 */ 00247 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) 00248 { 00249 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); 00250 } 00251 00252 /** 00253 * @brief Configures the SysTick clock source 00254 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource 00255 * @param Source This parameter can be one of the following values: 00256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00258 * @retval None 00259 */ 00260 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) 00261 { 00262 if (Source == LL_SYSTICK_CLKSOURCE_HCLK) 00263 { 00264 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00265 } 00266 else 00267 { 00268 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00269 } 00270 } 00271 00272 /** 00273 * @brief Get the SysTick clock source 00274 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource 00275 * @retval Returned value can be one of the following values: 00276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00278 */ 00279 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) 00280 { 00281 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00282 } 00283 00284 /** 00285 * @brief Enable SysTick exception request 00286 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT 00287 * @retval None 00288 */ 00289 __STATIC_INLINE void LL_SYSTICK_EnableIT(void) 00290 { 00291 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00292 } 00293 00294 /** 00295 * @brief Disable SysTick exception request 00296 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT 00297 * @retval None 00298 */ 00299 __STATIC_INLINE void LL_SYSTICK_DisableIT(void) 00300 { 00301 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00302 } 00303 00304 /** 00305 * @brief Checks if the SYSTICK interrupt is enabled or disabled. 00306 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT 00307 * @retval State of bit (1 or 0). 00308 */ 00309 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) 00310 { 00311 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); 00312 } 00313 00314 /** 00315 * @} 00316 */ 00317 00318 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE 00319 * @{ 00320 */ 00321 00322 /** 00323 * @brief Processor uses sleep as its low power mode 00324 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep 00325 * @retval None 00326 */ 00327 __STATIC_INLINE void LL_LPM_EnableSleep(void) 00328 { 00329 /* Clear SLEEPDEEP bit of Cortex System Control Register */ 00330 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00331 } 00332 00333 /** 00334 * @brief Processor uses deep sleep as its low power mode 00335 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep 00336 * @retval None 00337 */ 00338 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) 00339 { 00340 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00341 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00342 } 00343 00344 /** 00345 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. 00346 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an 00347 * empty main application. 00348 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit 00349 * @retval None 00350 */ 00351 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) 00352 { 00353 /* Set SLEEPONEXIT bit of Cortex System Control Register */ 00354 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00355 } 00356 00357 /** 00358 * @brief Do not sleep when returning to Thread mode. 00359 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit 00360 * @retval None 00361 */ 00362 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) 00363 { 00364 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 00365 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00366 } 00367 00368 /** 00369 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the 00370 * processor. 00371 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend 00372 * @retval None 00373 */ 00374 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) 00375 { 00376 /* Set SEVEONPEND bit of Cortex System Control Register */ 00377 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00378 } 00379 00380 /** 00381 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are 00382 * excluded 00383 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend 00384 * @retval None 00385 */ 00386 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) 00387 { 00388 /* Clear SEVEONPEND bit of Cortex System Control Register */ 00389 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00390 } 00391 00392 /** 00393 * @} 00394 */ 00395 00396 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER 00397 * @{ 00398 */ 00399 00400 /** 00401 * @brief Enable a fault in System handler control register (SHCSR) 00402 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault 00403 * @param Fault This parameter can be a combination of the following values: 00404 * @arg @ref LL_HANDLER_FAULT_USG 00405 * @arg @ref LL_HANDLER_FAULT_BUS 00406 * @arg @ref LL_HANDLER_FAULT_MEM 00407 * @retval None 00408 */ 00409 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) 00410 { 00411 /* Enable the system handler fault */ 00412 SET_BIT(SCB->SHCSR, Fault); 00413 } 00414 00415 /** 00416 * @brief Disable a fault in System handler control register (SHCSR) 00417 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault 00418 * @param Fault This parameter can be a combination of the following values: 00419 * @arg @ref LL_HANDLER_FAULT_USG 00420 * @arg @ref LL_HANDLER_FAULT_BUS 00421 * @arg @ref LL_HANDLER_FAULT_MEM 00422 * @retval None 00423 */ 00424 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) 00425 { 00426 /* Disable the system handler fault */ 00427 CLEAR_BIT(SCB->SHCSR, Fault); 00428 } 00429 00430 /** 00431 * @} 00432 */ 00433 00434 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO 00435 * @{ 00436 */ 00437 00438 /** 00439 * @brief Get Implementer code 00440 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer 00441 * @retval Value should be equal to 0x41 for ARM 00442 */ 00443 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) 00444 { 00445 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); 00446 } 00447 00448 /** 00449 * @brief Get Variant number (The r value in the rnpn product revision identifier) 00450 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant 00451 * @retval Value between 0 and 255 (0x0: revision 0) 00452 */ 00453 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) 00454 { 00455 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); 00456 } 00457 00458 /** 00459 * @brief Get Constant number 00460 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant 00461 * @retval Value should be equal to 0xF for Cortex-M4 devices 00462 */ 00463 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) 00464 { 00465 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); 00466 } 00467 00468 /** 00469 * @brief Get Part number 00470 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo 00471 * @retval Value should be equal to 0xC24 for Cortex-M4 00472 */ 00473 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) 00474 { 00475 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); 00476 } 00477 00478 /** 00479 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) 00480 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision 00481 * @retval Value between 0 and 255 (0x1: patch 1) 00482 */ 00483 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) 00484 { 00485 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); 00486 } 00487 00488 /** 00489 * @} 00490 */ 00491 00492 #if __MPU_PRESENT 00493 /** @defgroup CORTEX_LL_EF_MPU MPU 00494 * @{ 00495 */ 00496 00497 /** 00498 * @brief Enable MPU with input options 00499 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable 00500 * @param Options This parameter can be one of the following values: 00501 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 00502 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI 00503 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT 00504 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF 00505 * @retval None 00506 */ 00507 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) 00508 { 00509 /* Enable the MPU*/ 00510 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); 00511 /* Ensure MPU settings take effects */ 00512 __DSB(); 00513 /* Sequence instruction fetches using update settings */ 00514 __ISB(); 00515 } 00516 00517 /** 00518 * @brief Disable MPU 00519 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable 00520 * @retval None 00521 */ 00522 __STATIC_INLINE void LL_MPU_Disable(void) 00523 { 00524 /* Make sure outstanding transfers are done */ 00525 __DMB(); 00526 /* Disable MPU*/ 00527 WRITE_REG(MPU->CTRL, 0U); 00528 } 00529 00530 /** 00531 * @brief Check if MPU is enabled or not 00532 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled 00533 * @retval State of bit (1 or 0). 00534 */ 00535 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) 00536 { 00537 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); 00538 } 00539 00540 /** 00541 * @brief Enable a MPU region 00542 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion 00543 * @param Region This parameter can be one of the following values: 00544 * @arg @ref LL_MPU_REGION_NUMBER0 00545 * @arg @ref LL_MPU_REGION_NUMBER1 00546 * @arg @ref LL_MPU_REGION_NUMBER2 00547 * @arg @ref LL_MPU_REGION_NUMBER3 00548 * @arg @ref LL_MPU_REGION_NUMBER4 00549 * @arg @ref LL_MPU_REGION_NUMBER5 00550 * @arg @ref LL_MPU_REGION_NUMBER6 00551 * @arg @ref LL_MPU_REGION_NUMBER7 00552 * @retval None 00553 */ 00554 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) 00555 { 00556 /* Set Region number */ 00557 WRITE_REG(MPU->RNR, Region); 00558 /* Enable the MPU region */ 00559 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00560 } 00561 00562 /** 00563 * @brief Configure and enable a region 00564 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n 00565 * MPU_RBAR REGION LL_MPU_ConfigRegion\n 00566 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n 00567 * MPU_RASR XN LL_MPU_ConfigRegion\n 00568 * MPU_RASR AP LL_MPU_ConfigRegion\n 00569 * MPU_RASR S LL_MPU_ConfigRegion\n 00570 * MPU_RASR C LL_MPU_ConfigRegion\n 00571 * MPU_RASR B LL_MPU_ConfigRegion\n 00572 * MPU_RASR SIZE LL_MPU_ConfigRegion 00573 * @param Region This parameter can be one of the following values: 00574 * @arg @ref LL_MPU_REGION_NUMBER0 00575 * @arg @ref LL_MPU_REGION_NUMBER1 00576 * @arg @ref LL_MPU_REGION_NUMBER2 00577 * @arg @ref LL_MPU_REGION_NUMBER3 00578 * @arg @ref LL_MPU_REGION_NUMBER4 00579 * @arg @ref LL_MPU_REGION_NUMBER5 00580 * @arg @ref LL_MPU_REGION_NUMBER6 00581 * @arg @ref LL_MPU_REGION_NUMBER7 00582 * @param Address Value of region base address 00583 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF 00584 * @param Attributes This parameter can be a combination of the following values: 00585 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B 00586 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB 00587 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB 00588 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB 00589 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB 00590 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB 00591 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS 00592 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO 00593 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 00594 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE 00595 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE 00596 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE 00597 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE 00598 * @retval None 00599 */ 00600 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) 00601 { 00602 /* Set Region number */ 00603 WRITE_REG(MPU->RNR, Region); 00604 /* Set base address */ 00605 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); 00606 /* Configure MPU */ 00607 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); 00608 } 00609 00610 /** 00611 * @brief Disable a region 00612 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n 00613 * MPU_RASR ENABLE LL_MPU_DisableRegion 00614 * @param Region This parameter can be one of the following values: 00615 * @arg @ref LL_MPU_REGION_NUMBER0 00616 * @arg @ref LL_MPU_REGION_NUMBER1 00617 * @arg @ref LL_MPU_REGION_NUMBER2 00618 * @arg @ref LL_MPU_REGION_NUMBER3 00619 * @arg @ref LL_MPU_REGION_NUMBER4 00620 * @arg @ref LL_MPU_REGION_NUMBER5 00621 * @arg @ref LL_MPU_REGION_NUMBER6 00622 * @arg @ref LL_MPU_REGION_NUMBER7 00623 * @retval None 00624 */ 00625 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) 00626 { 00627 /* Set Region number */ 00628 WRITE_REG(MPU->RNR, Region); 00629 /* Disable the MPU region */ 00630 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00631 } 00632 00633 /** 00634 * @} 00635 */ 00636 00637 #endif /* __MPU_PRESENT */ 00638 /** 00639 * @} 00640 */ 00641 00642 /** 00643 * @} 00644 */ 00645 00646 /** 00647 * @} 00648 */ 00649 00650 #ifdef __cplusplus 00651 } 00652 #endif 00653 00654 #endif /* __STM32F4xx_LL_CORTEX_H */ 00655 00656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/