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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @brief Header file of BUS LL module. 00006 00007 @verbatim 00008 ##### RCC Limitations ##### 00009 ============================================================================== 00010 [..] 00011 A delay between an RCC peripheral clock enable and the effective peripheral 00012 enabling should be taken into account in order to manage the peripheral read/write 00013 from/to registers. 00014 (+) This delay depends on the peripheral mapping. 00015 (++) AHB & APB peripherals, 1 dummy read is necessary 00016 00017 [..] 00018 Workarounds: 00019 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00020 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 00021 00022 @endverbatim 00023 ****************************************************************************** 00024 * @attention 00025 * 00026 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00027 * 00028 * Redistribution and use in source and binary forms, with or without modification, 00029 * are permitted provided that the following conditions are met: 00030 * 1. Redistributions of source code must retain the above copyright notice, 00031 * this list of conditions and the following disclaimer. 00032 * 2. Redistributions in binary form must reproduce the above copyright notice, 00033 * this list of conditions and the following disclaimer in the documentation 00034 * and/or other materials provided with the distribution. 00035 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00036 * may be used to endorse or promote products derived from this software 00037 * without specific prior written permission. 00038 * 00039 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00040 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00041 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00042 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00043 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00044 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00045 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00046 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00047 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00048 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00049 * 00050 ****************************************************************************** 00051 */ 00052 00053 /* Define to prevent recursive inclusion -------------------------------------*/ 00054 #ifndef __STM32F4xx_LL_BUS_H 00055 #define __STM32F4xx_LL_BUS_H 00056 00057 #ifdef __cplusplus 00058 extern "C" { 00059 #endif 00060 00061 /* Includes ------------------------------------------------------------------*/ 00062 #include "stm32f4xx.h" 00063 00064 /** @addtogroup STM32F4xx_LL_Driver 00065 * @{ 00066 */ 00067 00068 #if defined(RCC) 00069 00070 /** @defgroup BUS_LL BUS 00071 * @{ 00072 */ 00073 00074 /* Private types -------------------------------------------------------------*/ 00075 /* Private variables ---------------------------------------------------------*/ 00076 /* Private constants ---------------------------------------------------------*/ 00077 /* Private macros ------------------------------------------------------------*/ 00078 /* Exported types ------------------------------------------------------------*/ 00079 /* Exported constants --------------------------------------------------------*/ 00080 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00081 * @{ 00082 */ 00083 00084 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00085 * @{ 00086 */ 00087 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00088 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN 00089 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN 00090 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN 00091 #if defined(GPIOD) 00092 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN 00093 #endif /* GPIOD */ 00094 #if defined(GPIOE) 00095 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN 00096 #endif /* GPIOE */ 00097 #if defined(GPIOF) 00098 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN 00099 #endif /* GPIOF */ 00100 #if defined(GPIOG) 00101 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN 00102 #endif /* GPIOG */ 00103 #if defined(GPIOH) 00104 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN 00105 #endif /* GPIOH */ 00106 #if defined(GPIOI) 00107 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN 00108 #endif /* GPIOI */ 00109 #if defined(GPIOJ) 00110 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN 00111 #endif /* GPIOJ */ 00112 #if defined(GPIOK) 00113 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN 00114 #endif /* GPIOK */ 00115 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 00116 #if defined(RCC_AHB1ENR_BKPSRAMEN) 00117 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN 00118 #endif /* RCC_AHB1ENR_BKPSRAMEN */ 00119 #if defined(RCC_AHB1ENR_CCMDATARAMEN) 00120 #define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN 00121 #endif /* RCC_AHB1ENR_CCMDATARAMEN */ 00122 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 00123 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 00124 #if defined(RCC_AHB1ENR_RNGEN) 00125 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN 00126 #endif /* RCC_AHB1ENR_RNGEN */ 00127 #if defined(DMA2D) 00128 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN 00129 #endif /* DMA2D */ 00130 #if defined(ETH) 00131 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN 00132 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN 00133 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN 00134 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN 00135 #endif /* ETH */ 00136 #if defined(USB_OTG_HS) 00137 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN 00138 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN 00139 #endif /* USB_OTG_HS */ 00140 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN 00141 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN 00142 #if defined(RCC_AHB1LPENR_SRAM2LPEN) 00143 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN 00144 #endif /* RCC_AHB1LPENR_SRAM2LPEN */ 00145 #if defined(RCC_AHB1LPENR_SRAM3LPEN) 00146 #define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN 00147 #endif /* RCC_AHB1LPENR_SRAM3LPEN */ 00148 /** 00149 * @} 00150 */ 00151 00152 #if defined(RCC_AHB2_SUPPORT) 00153 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 00154 * @{ 00155 */ 00156 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00157 #if defined(DCMI) 00158 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 00159 #endif /* DCMI */ 00160 #if defined(CRYP) 00161 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN 00162 #endif /* CRYP */ 00163 #if defined(AES) 00164 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 00165 #endif /* AES */ 00166 #if defined(HASH) 00167 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 00168 #endif /* HASH */ 00169 #if defined(RCC_AHB2ENR_RNGEN) 00170 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 00171 #endif /* RCC_AHB2ENR_RNGEN */ 00172 #if defined(USB_OTG_FS) 00173 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 00174 #endif /* USB_OTG_FS */ 00175 /** 00176 * @} 00177 */ 00178 #endif /* RCC_AHB2_SUPPORT */ 00179 00180 #if defined(RCC_AHB3_SUPPORT) 00181 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 00182 * @{ 00183 */ 00184 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 00185 #if defined(FSMC_Bank1) 00186 #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN 00187 #endif /* FSMC_Bank1 */ 00188 #if defined(FMC_Bank1) 00189 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 00190 #endif /* FMC_Bank1 */ 00191 #if defined(QUADSPI) 00192 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 00193 #endif /* QUADSPI */ 00194 /** 00195 * @} 00196 */ 00197 #endif /* RCC_AHB3_SUPPORT */ 00198 00199 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00200 * @{ 00201 */ 00202 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00203 #if defined(TIM2) 00204 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN 00205 #endif /* TIM2 */ 00206 #if defined(TIM3) 00207 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN 00208 #endif /* TIM3 */ 00209 #if defined(TIM4) 00210 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN 00211 #endif /* TIM4 */ 00212 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN 00213 #if defined(TIM6) 00214 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN 00215 #endif /* TIM6 */ 00216 #if defined(TIM7) 00217 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN 00218 #endif /* TIM7 */ 00219 #if defined(TIM12) 00220 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN 00221 #endif /* TIM12 */ 00222 #if defined(TIM13) 00223 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN 00224 #endif /* TIM13 */ 00225 #if defined(TIM14) 00226 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN 00227 #endif /* TIM14 */ 00228 #if defined(LPTIM1) 00229 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN 00230 #endif /* LPTIM1 */ 00231 #if defined(RCC_APB1ENR_RTCAPBEN) 00232 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN 00233 #endif /* RCC_APB1ENR_RTCAPBEN */ 00234 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN 00235 #if defined(SPI2) 00236 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN 00237 #endif /* SPI2 */ 00238 #if defined(SPI3) 00239 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN 00240 #endif /* SPI3 */ 00241 #if defined(SPDIFRX) 00242 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN 00243 #endif /* SPDIFRX */ 00244 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN 00245 #if defined(USART3) 00246 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN 00247 #endif /* USART3 */ 00248 #if defined(UART4) 00249 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN 00250 #endif /* UART4 */ 00251 #if defined(UART5) 00252 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN 00253 #endif /* UART5 */ 00254 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN 00255 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN 00256 #if defined(I2C3) 00257 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN 00258 #endif /* I2C3 */ 00259 #if defined(FMPI2C1) 00260 #define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN 00261 #endif /* FMPI2C1 */ 00262 #if defined(CAN1) 00263 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN 00264 #endif /* CAN1 */ 00265 #if defined(CAN2) 00266 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN 00267 #endif /* CAN2 */ 00268 #if defined(CAN3) 00269 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN 00270 #endif /* CAN3 */ 00271 #if defined(CEC) 00272 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN 00273 #endif /* CEC */ 00274 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN 00275 #if defined(DAC1) 00276 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN 00277 #endif /* DAC1 */ 00278 #if defined(UART7) 00279 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN 00280 #endif /* UART7 */ 00281 #if defined(UART8) 00282 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN 00283 #endif /* UART8 */ 00284 /** 00285 * @} 00286 */ 00287 00288 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 00289 * @{ 00290 */ 00291 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00292 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 00293 #if defined(TIM8) 00294 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 00295 #endif /* TIM8 */ 00296 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 00297 #if defined(USART6) 00298 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN 00299 #endif /* USART6 */ 00300 #if defined(UART9) 00301 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN 00302 #endif /* UART9 */ 00303 #if defined(UART10) 00304 #define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN 00305 #endif /* UART10 */ 00306 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN 00307 #if defined(ADC2) 00308 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN 00309 #endif /* ADC2 */ 00310 #if defined(ADC3) 00311 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN 00312 #endif /* ADC3 */ 00313 #if defined(SDIO) 00314 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN 00315 #endif /* SDIO */ 00316 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 00317 #if defined(SPI4) 00318 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN 00319 #endif /* SPI4 */ 00320 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 00321 #if defined(RCC_APB2ENR_EXTITEN) 00322 #define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN 00323 #endif /* RCC_APB2ENR_EXTITEN */ 00324 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN 00325 #if defined(TIM10) 00326 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN 00327 #endif /* TIM10 */ 00328 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN 00329 #if defined(SPI5) 00330 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN 00331 #endif /* SPI5 */ 00332 #if defined(SPI6) 00333 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN 00334 #endif /* SPI6 */ 00335 #if defined(SAI1) 00336 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 00337 #endif /* SAI1 */ 00338 #if defined(SAI2) 00339 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 00340 #endif /* SAI2 */ 00341 #if defined(LTDC) 00342 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN 00343 #endif /* LTDC */ 00344 #if defined(DSI) 00345 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN 00346 #endif /* DSI */ 00347 #if defined(DFSDM1_Channel0) 00348 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 00349 #endif /* DFSDM1_Channel0 */ 00350 #if defined(DFSDM2_Channel0) 00351 #define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN 00352 #endif /* DFSDM2_Channel0 */ 00353 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST 00354 /** 00355 * @} 00356 */ 00357 00358 /** 00359 * @} 00360 */ 00361 00362 /* Exported macro ------------------------------------------------------------*/ 00363 /* Exported functions --------------------------------------------------------*/ 00364 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 00365 * @{ 00366 */ 00367 00368 /** @defgroup BUS_LL_EF_AHB1 AHB1 00369 * @{ 00370 */ 00371 00372 /** 00373 * @brief Enable AHB1 peripherals clock. 00374 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n 00375 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n 00376 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n 00377 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n 00378 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n 00379 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n 00380 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n 00381 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n 00382 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n 00383 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n 00384 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n 00385 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 00386 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n 00387 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n 00388 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 00389 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 00390 * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n 00391 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n 00392 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n 00393 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n 00394 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n 00395 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n 00396 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n 00397 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock 00398 * @param Periphs This parameter can be a combination of the following values: 00399 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00400 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00401 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00402 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00403 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00404 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00405 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00406 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00407 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00410 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00411 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00412 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) 00413 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00414 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00415 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00416 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00417 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00418 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00419 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00420 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00421 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00422 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00423 * 00424 * (*) value not defined in all devices. 00425 * @retval None 00426 */ 00427 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 00428 { 00429 __IO uint32_t tmpreg; 00430 SET_BIT(RCC->AHB1ENR, Periphs); 00431 /* Delay after an RCC peripheral clock enabling */ 00432 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 00433 (void)tmpreg; 00434 } 00435 00436 /** 00437 * @brief Check if AHB1 peripheral clock is enabled or not 00438 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n 00439 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n 00440 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n 00441 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n 00442 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n 00443 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n 00444 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n 00445 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n 00446 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n 00447 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n 00448 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n 00449 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 00450 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n 00451 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n 00452 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 00453 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 00454 * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n 00455 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n 00456 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n 00457 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n 00458 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n 00459 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n 00460 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n 00461 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock 00462 * @param Periphs This parameter can be a combination of the following values: 00463 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00464 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00465 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00466 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00467 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00468 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00469 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00470 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00471 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00472 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00473 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00474 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00475 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00476 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) 00477 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00478 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00479 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00480 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00481 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00482 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00483 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00484 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00485 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00486 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00487 * 00488 * (*) value not defined in all devices. 00489 * @retval State of Periphs (1 or 0). 00490 */ 00491 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 00492 { 00493 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); 00494 } 00495 00496 /** 00497 * @brief Disable AHB1 peripherals clock. 00498 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n 00499 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n 00500 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n 00501 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n 00502 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n 00503 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n 00504 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n 00505 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n 00506 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n 00507 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n 00508 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n 00509 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 00510 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n 00511 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n 00512 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 00513 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 00514 * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n 00515 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n 00516 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n 00517 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n 00518 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n 00519 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n 00520 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n 00521 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock 00522 * @param Periphs This parameter can be a combination of the following values: 00523 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00524 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00525 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00526 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00527 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00528 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00529 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00530 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00531 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00532 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00533 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00534 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00535 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00536 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) 00537 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00538 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00539 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00540 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00541 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00542 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00543 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00544 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00545 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00546 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00547 * 00548 * (*) value not defined in all devices. 00549 * @retval None 00550 */ 00551 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 00552 { 00553 CLEAR_BIT(RCC->AHB1ENR, Periphs); 00554 } 00555 00556 /** 00557 * @brief Force AHB1 peripherals reset. 00558 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n 00559 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n 00560 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n 00561 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n 00562 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n 00563 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n 00564 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n 00565 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n 00566 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n 00567 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n 00568 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n 00569 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 00570 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 00571 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 00572 * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n 00573 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n 00574 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n 00575 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset 00576 * @param Periphs This parameter can be a combination of the following values: 00577 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00578 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00579 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00580 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00581 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00582 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00583 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00584 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00585 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00586 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00587 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00588 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00589 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00590 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00591 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00592 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00593 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00594 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00595 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00596 * 00597 * (*) value not defined in all devices. 00598 * @retval None 00599 */ 00600 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 00601 { 00602 SET_BIT(RCC->AHB1RSTR, Periphs); 00603 } 00604 00605 /** 00606 * @brief Release AHB1 peripherals reset. 00607 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n 00608 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n 00609 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n 00610 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n 00611 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n 00612 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n 00613 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n 00614 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n 00615 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n 00616 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n 00617 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n 00618 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 00619 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 00620 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 00621 * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n 00622 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n 00623 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n 00624 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset 00625 * @param Periphs This parameter can be a combination of the following values: 00626 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00627 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00628 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00629 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00630 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00631 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00632 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00633 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00634 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00635 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00636 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00637 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00638 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00639 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00640 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00641 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00642 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00643 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00644 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00645 * 00646 * (*) value not defined in all devices. 00647 * @retval None 00648 */ 00649 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 00650 { 00651 CLEAR_BIT(RCC->AHB1RSTR, Periphs); 00652 } 00653 00654 /** 00655 * @brief Enable AHB1 peripheral clocks in low-power mode 00656 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n 00657 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00658 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00659 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00660 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n 00661 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00662 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00663 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00664 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n 00665 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00666 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00667 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00668 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00669 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00670 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00671 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00672 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00673 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00674 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00675 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n 00676 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00677 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00678 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00679 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00680 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00681 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00682 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n 00683 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower 00684 * @param Periphs This parameter can be a combination of the following values: 00685 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00686 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00687 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00688 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00689 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00690 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00691 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00692 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00693 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00694 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00695 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00696 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00697 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00698 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 00699 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00700 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) 00701 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) 00702 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00703 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00704 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00705 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00706 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00707 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00708 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00709 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00710 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00711 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00712 * 00713 * (*) value not defined in all devices. 00714 * @retval None 00715 */ 00716 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) 00717 { 00718 __IO uint32_t tmpreg; 00719 SET_BIT(RCC->AHB1LPENR, Periphs); 00720 /* Delay after an RCC peripheral clock enabling */ 00721 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); 00722 (void)tmpreg; 00723 } 00724 00725 /** 00726 * @brief Disable AHB1 peripheral clocks in low-power mode 00727 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n 00728 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00729 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00730 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00731 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n 00732 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00733 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00734 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00735 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n 00736 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00737 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00738 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00739 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00740 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00741 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00742 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00743 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00744 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00745 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00746 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n 00747 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00748 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00749 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00750 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00751 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00752 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00753 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n 00754 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower 00755 * @param Periphs This parameter can be a combination of the following values: 00756 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA 00757 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB 00758 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC 00759 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) 00760 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) 00761 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) 00762 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) 00763 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) 00764 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) 00765 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) 00766 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) 00767 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00768 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) 00769 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF 00770 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00771 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) 00772 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) 00773 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00774 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00775 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) 00776 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00777 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00778 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00779 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00780 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) 00781 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) 00782 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) 00783 * 00784 * (*) value not defined in all devices. 00785 * @retval None 00786 */ 00787 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) 00788 { 00789 CLEAR_BIT(RCC->AHB1LPENR, Periphs); 00790 } 00791 00792 /** 00793 * @} 00794 */ 00795 00796 #if defined(RCC_AHB2_SUPPORT) 00797 /** @defgroup BUS_LL_EF_AHB2 AHB2 00798 * @{ 00799 */ 00800 00801 /** 00802 * @brief Enable AHB2 peripherals clock. 00803 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 00804 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n 00805 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 00806 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n 00807 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 00808 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock 00809 * @param Periphs This parameter can be a combination of the following values: 00810 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00811 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00812 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00813 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00814 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00815 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00816 * 00817 * (*) value not defined in all devices. 00818 * @retval None 00819 */ 00820 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 00821 { 00822 __IO uint32_t tmpreg; 00823 SET_BIT(RCC->AHB2ENR, Periphs); 00824 /* Delay after an RCC peripheral clock enabling */ 00825 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 00826 (void)tmpreg; 00827 } 00828 00829 /** 00830 * @brief Check if AHB2 peripheral clock is enabled or not 00831 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 00832 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n 00833 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 00834 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n 00835 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 00836 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock 00837 * @param Periphs This parameter can be a combination of the following values: 00838 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00839 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00840 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00841 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00842 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00843 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00844 * 00845 * (*) value not defined in all devices. 00846 * @retval State of Periphs (1 or 0). 00847 */ 00848 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 00849 { 00850 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 00851 } 00852 00853 /** 00854 * @brief Disable AHB2 peripherals clock. 00855 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 00856 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n 00857 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 00858 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n 00859 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 00860 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock 00861 * @param Periphs This parameter can be a combination of the following values: 00862 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00863 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00864 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00865 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00866 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00867 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00868 * 00869 * (*) value not defined in all devices. 00870 * @retval None 00871 */ 00872 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 00873 { 00874 CLEAR_BIT(RCC->AHB2ENR, Periphs); 00875 } 00876 00877 /** 00878 * @brief Force AHB2 peripherals reset. 00879 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 00880 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n 00881 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 00882 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n 00883 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 00884 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset 00885 * @param Periphs This parameter can be a combination of the following values: 00886 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00887 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00888 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00889 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00890 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00891 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00892 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00893 * 00894 * (*) value not defined in all devices. 00895 * @retval None 00896 */ 00897 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 00898 { 00899 SET_BIT(RCC->AHB2RSTR, Periphs); 00900 } 00901 00902 /** 00903 * @brief Release AHB2 peripherals reset. 00904 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 00905 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n 00906 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 00907 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n 00908 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 00909 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset 00910 * @param Periphs This parameter can be a combination of the following values: 00911 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00912 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00913 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00914 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00915 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00916 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00917 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00918 * 00919 * (*) value not defined in all devices. 00920 * @retval None 00921 */ 00922 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 00923 { 00924 CLEAR_BIT(RCC->AHB2RSTR, Periphs); 00925 } 00926 00927 /** 00928 * @brief Enable AHB2 peripheral clocks in low-power mode 00929 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n 00930 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n 00931 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n 00932 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n 00933 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n 00934 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower 00935 * @param Periphs This parameter can be a combination of the following values: 00936 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00937 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00938 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00939 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00940 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00941 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00942 * 00943 * (*) value not defined in all devices. 00944 * @retval None 00945 */ 00946 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) 00947 { 00948 __IO uint32_t tmpreg; 00949 SET_BIT(RCC->AHB2LPENR, Periphs); 00950 /* Delay after an RCC peripheral clock enabling */ 00951 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); 00952 (void)tmpreg; 00953 } 00954 00955 /** 00956 * @brief Disable AHB2 peripheral clocks in low-power mode 00957 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n 00958 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n 00959 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n 00960 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n 00961 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n 00962 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower 00963 * @param Periphs This parameter can be a combination of the following values: 00964 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00965 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 00966 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00967 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00968 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) 00969 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00970 * 00971 * (*) value not defined in all devices. 00972 * @retval None 00973 */ 00974 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) 00975 { 00976 CLEAR_BIT(RCC->AHB2LPENR, Periphs); 00977 } 00978 00979 /** 00980 * @} 00981 */ 00982 #endif /* RCC_AHB2_SUPPORT */ 00983 00984 #if defined(RCC_AHB3_SUPPORT) 00985 /** @defgroup BUS_LL_EF_AHB3 AHB3 00986 * @{ 00987 */ 00988 00989 /** 00990 * @brief Enable AHB3 peripherals clock. 00991 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 00992 * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n 00993 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock 00994 * @param Periphs This parameter can be a combination of the following values: 00995 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00996 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 00997 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00998 * 00999 * (*) value not defined in all devices. 01000 * @retval None 01001 */ 01002 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 01003 { 01004 __IO uint32_t tmpreg; 01005 SET_BIT(RCC->AHB3ENR, Periphs); 01006 /* Delay after an RCC peripheral clock enabling */ 01007 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 01008 (void)tmpreg; 01009 } 01010 01011 /** 01012 * @brief Check if AHB3 peripheral clock is enabled or not 01013 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 01014 * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n 01015 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock 01016 * @param Periphs This parameter can be a combination of the following values: 01017 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01018 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01019 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01020 * 01021 * (*) value not defined in all devices. 01022 * @retval State of Periphs (1 or 0). 01023 */ 01024 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 01025 { 01026 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 01027 } 01028 01029 /** 01030 * @brief Disable AHB3 peripherals clock. 01031 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 01032 * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n 01033 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock 01034 * @param Periphs This parameter can be a combination of the following values: 01035 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01036 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01037 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01038 * 01039 * (*) value not defined in all devices. 01040 * @retval None 01041 */ 01042 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 01043 { 01044 CLEAR_BIT(RCC->AHB3ENR, Periphs); 01045 } 01046 01047 /** 01048 * @brief Force AHB3 peripherals reset. 01049 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 01050 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n 01051 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset 01052 * @param Periphs This parameter can be a combination of the following values: 01053 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 01054 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01055 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01056 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01057 * 01058 * (*) value not defined in all devices. 01059 * @retval None 01060 */ 01061 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 01062 { 01063 SET_BIT(RCC->AHB3RSTR, Periphs); 01064 } 01065 01066 /** 01067 * @brief Release AHB3 peripherals reset. 01068 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 01069 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n 01070 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset 01071 * @param Periphs This parameter can be a combination of the following values: 01072 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 01073 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01074 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01075 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01076 * 01077 * (*) value not defined in all devices. 01078 * @retval None 01079 */ 01080 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 01081 { 01082 CLEAR_BIT(RCC->AHB3RSTR, Periphs); 01083 } 01084 01085 /** 01086 * @brief Enable AHB3 peripheral clocks in low-power mode 01087 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n 01088 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n 01089 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower 01090 * @param Periphs This parameter can be a combination of the following values: 01091 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01092 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01093 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01094 * 01095 * (*) value not defined in all devices. 01096 * @retval None 01097 */ 01098 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) 01099 { 01100 __IO uint32_t tmpreg; 01101 SET_BIT(RCC->AHB3LPENR, Periphs); 01102 /* Delay after an RCC peripheral clock enabling */ 01103 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); 01104 (void)tmpreg; 01105 } 01106 01107 /** 01108 * @brief Disable AHB3 peripheral clocks in low-power mode 01109 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n 01110 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n 01111 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower 01112 * @param Periphs This parameter can be a combination of the following values: 01113 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01114 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) 01115 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01116 * 01117 * (*) value not defined in all devices. 01118 * @retval None 01119 */ 01120 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) 01121 { 01122 CLEAR_BIT(RCC->AHB3LPENR, Periphs); 01123 } 01124 01125 /** 01126 * @} 01127 */ 01128 #endif /* RCC_AHB3_SUPPORT */ 01129 01130 /** @defgroup BUS_LL_EF_APB1 APB1 01131 * @{ 01132 */ 01133 01134 /** 01135 * @brief Enable APB1 peripherals clock. 01136 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n 01137 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n 01138 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n 01139 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n 01140 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n 01141 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n 01142 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n 01143 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n 01144 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n 01145 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n 01146 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n 01147 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n 01148 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n 01149 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n 01150 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n 01151 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n 01152 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n 01153 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n 01154 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n 01155 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n 01156 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n 01157 * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n 01158 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n 01159 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n 01160 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n 01161 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n 01162 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n 01163 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n 01164 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n 01165 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n 01166 * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock 01167 * @param Periphs This parameter can be a combination of the following values: 01168 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01169 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01170 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01171 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01172 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01173 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01174 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01175 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01176 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01177 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01178 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01179 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01180 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01181 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01182 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01183 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01184 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01185 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01186 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01187 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01188 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01189 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01190 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01191 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01192 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01193 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01194 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01195 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01196 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01197 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01198 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01199 * 01200 * (*) value not defined in all devices. 01201 * @retval None 01202 */ 01203 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 01204 { 01205 __IO uint32_t tmpreg; 01206 SET_BIT(RCC->APB1ENR, Periphs); 01207 /* Delay after an RCC peripheral clock enabling */ 01208 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 01209 (void)tmpreg; 01210 } 01211 01212 /** 01213 * @brief Check if APB1 peripheral clock is enabled or not 01214 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 01215 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 01216 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n 01217 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 01218 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 01219 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 01220 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 01221 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 01222 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 01223 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n 01224 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n 01225 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 01226 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 01227 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n 01228 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 01229 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 01230 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 01231 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 01232 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 01233 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 01234 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n 01235 * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n 01236 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n 01237 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n 01238 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n 01239 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n 01240 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n 01241 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n 01242 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n 01243 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n 01244 * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock 01245 * @param Periphs This parameter can be a combination of the following values: 01246 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01247 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01248 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01249 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01250 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01251 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01252 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01253 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01254 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01255 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01256 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01257 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01258 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01259 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01260 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01261 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01262 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01263 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01264 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01265 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01266 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01267 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01268 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01269 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01270 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01271 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01272 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01273 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01274 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01275 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01276 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01277 * 01278 * (*) value not defined in all devices. 01279 * @retval State of Periphs (1 or 0). 01280 */ 01281 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 01282 { 01283 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); 01284 } 01285 01286 /** 01287 * @brief Disable APB1 peripherals clock. 01288 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n 01289 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n 01290 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n 01291 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n 01292 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n 01293 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n 01294 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n 01295 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n 01296 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n 01297 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n 01298 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n 01299 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n 01300 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n 01301 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n 01302 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n 01303 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n 01304 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n 01305 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n 01306 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n 01307 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n 01308 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n 01309 * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n 01310 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n 01311 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n 01312 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n 01313 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n 01314 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n 01315 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n 01316 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n 01317 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n 01318 * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock 01319 * @param Periphs This parameter can be a combination of the following values: 01320 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01321 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01322 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01323 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01324 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01325 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01326 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01327 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01328 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01329 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01330 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01331 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01332 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01333 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01334 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01335 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01336 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01337 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01338 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01339 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01340 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01341 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01342 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01343 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01344 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01345 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01346 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01347 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01348 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01349 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01350 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01351 * 01352 * (*) value not defined in all devices. 01353 * @retval None 01354 */ 01355 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 01356 { 01357 CLEAR_BIT(RCC->APB1ENR, Periphs); 01358 } 01359 01360 /** 01361 * @brief Force APB1 peripherals reset. 01362 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n 01363 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n 01364 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n 01365 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n 01366 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n 01367 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n 01368 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n 01369 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n 01370 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n 01371 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n 01372 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n 01373 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n 01374 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n 01375 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n 01376 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n 01377 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n 01378 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n 01379 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n 01380 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n 01381 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n 01382 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n 01383 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n 01384 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n 01385 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n 01386 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n 01387 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n 01388 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n 01389 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n 01390 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n 01391 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset 01392 * @param Periphs This parameter can be a combination of the following values: 01393 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01394 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01395 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01396 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01397 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01398 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01399 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01402 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01403 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01404 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01405 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01406 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01407 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01408 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01409 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01410 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01411 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01412 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01413 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01414 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01415 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01416 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01417 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01418 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01419 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01420 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01421 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01422 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01423 * 01424 * (*) value not defined in all devices. 01425 * @retval None 01426 */ 01427 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 01428 { 01429 SET_BIT(RCC->APB1RSTR, Periphs); 01430 } 01431 01432 /** 01433 * @brief Release APB1 peripherals reset. 01434 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 01435 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 01436 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 01437 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 01438 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 01439 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 01440 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 01441 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 01442 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 01443 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n 01444 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n 01445 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 01446 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 01447 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n 01448 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 01449 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 01450 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 01451 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 01452 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 01453 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 01454 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n 01455 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n 01456 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n 01457 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n 01458 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n 01459 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n 01460 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n 01461 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n 01462 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n 01463 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset 01464 * @param Periphs This parameter can be a combination of the following values: 01465 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01466 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01467 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01468 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01469 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01470 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01471 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01472 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01473 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01474 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01475 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01476 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01477 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01478 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01479 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01480 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01481 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01482 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01483 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01484 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01485 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01486 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01487 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01488 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01489 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01490 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01491 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01492 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01493 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01494 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01495 * 01496 * (*) value not defined in all devices. 01497 * @retval None 01498 */ 01499 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 01500 { 01501 CLEAR_BIT(RCC->APB1RSTR, Periphs); 01502 } 01503 01504 /** 01505 * @brief Enable APB1 peripheral clocks in low-power mode 01506 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01507 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01508 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n 01509 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n 01510 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n 01511 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n 01512 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n 01513 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n 01514 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n 01515 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n 01516 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n 01517 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01518 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01519 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n 01520 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01521 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01522 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n 01523 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n 01524 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n 01525 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01526 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01527 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n 01528 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n 01529 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n 01530 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n 01531 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n 01532 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n 01533 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n 01534 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n 01535 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n 01536 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower 01537 * @param Periphs This parameter can be a combination of the following values: 01538 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01539 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01540 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01541 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01542 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01543 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01544 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01545 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01546 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01547 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01548 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01549 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01550 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01551 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01552 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01553 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01554 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01555 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01556 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01557 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01558 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01559 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01560 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01561 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01562 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01563 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01564 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01565 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01566 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01567 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01568 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01569 * 01570 * (*) value not defined in all devices. 01571 * @retval None 01572 */ 01573 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) 01574 { 01575 __IO uint32_t tmpreg; 01576 SET_BIT(RCC->APB1LPENR, Periphs); 01577 /* Delay after an RCC peripheral clock enabling */ 01578 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); 01579 (void)tmpreg; 01580 } 01581 01582 /** 01583 * @brief Disable APB1 peripheral clocks in low-power mode 01584 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01585 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01586 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n 01587 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n 01588 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n 01589 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n 01590 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n 01591 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n 01592 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n 01593 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n 01594 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n 01595 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01596 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01597 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n 01598 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01599 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01600 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n 01601 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n 01602 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n 01603 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01604 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01605 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n 01606 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n 01607 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n 01608 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n 01609 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n 01610 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n 01611 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n 01612 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n 01613 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n 01614 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower 01615 * @param Periphs This parameter can be a combination of the following values: 01616 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) 01617 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 01620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 01621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 01622 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 01623 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 01624 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 01625 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) 01626 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01627 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01628 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 01629 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) 01630 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01631 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01632 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01633 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01634 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01635 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 01636 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) 01637 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) 01638 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 01639 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01640 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) 01641 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 01642 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01643 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 01644 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) 01645 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) 01646 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01647 * 01648 * (*) value not defined in all devices. 01649 * @retval None 01650 */ 01651 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) 01652 { 01653 CLEAR_BIT(RCC->APB1LPENR, Periphs); 01654 } 01655 01656 /** 01657 * @} 01658 */ 01659 01660 /** @defgroup BUS_LL_EF_APB2 APB2 01661 * @{ 01662 */ 01663 01664 /** 01665 * @brief Enable APB2 peripherals clock. 01666 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 01667 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 01668 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 01669 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n 01670 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n 01671 * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n 01672 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n 01673 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n 01674 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n 01675 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n 01676 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 01677 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n 01678 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 01679 * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n 01680 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n 01681 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n 01682 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n 01683 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n 01684 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n 01685 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 01686 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 01687 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n 01688 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n 01689 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 01690 * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock 01691 * @param Periphs This parameter can be a combination of the following values: 01692 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01693 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01694 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01695 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01696 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01697 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01698 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 01699 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 01700 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 01701 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01702 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01703 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01704 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01705 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01706 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01707 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01708 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01709 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01710 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01711 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01712 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01713 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01714 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01715 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01716 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01717 01718 * 01719 * (*) value not defined in all devices. 01720 * @retval None 01721 */ 01722 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 01723 { 01724 __IO uint32_t tmpreg; 01725 SET_BIT(RCC->APB2ENR, Periphs); 01726 /* Delay after an RCC peripheral clock enabling */ 01727 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 01728 (void)tmpreg; 01729 } 01730 01731 /** 01732 * @brief Check if APB2 peripheral clock is enabled or not 01733 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 01734 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 01735 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n 01736 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n 01737 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n 01738 * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n 01739 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n 01740 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n 01741 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n 01742 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n 01743 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 01744 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n 01745 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n 01746 * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n 01747 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n 01748 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n 01749 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n 01750 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n 01751 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n 01752 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n 01753 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n 01754 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n 01755 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n 01756 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n 01757 * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock 01758 * @param Periphs This parameter can be a combination of the following values: 01759 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01760 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01761 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01762 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01763 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01764 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01765 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 01766 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 01767 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 01768 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01769 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01770 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01771 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01772 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01773 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01774 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01775 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01776 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01777 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01778 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01779 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01780 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01781 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01782 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01783 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01784 * 01785 * (*) value not defined in all devices. 01786 * @retval State of Periphs (1 or 0). 01787 */ 01788 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 01789 { 01790 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); 01791 } 01792 01793 /** 01794 * @brief Disable APB2 peripherals clock. 01795 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 01796 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 01797 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n 01798 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n 01799 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n 01800 * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n 01801 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n 01802 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n 01803 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n 01804 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n 01805 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 01806 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n 01807 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n 01808 * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n 01809 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n 01810 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n 01811 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n 01812 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n 01813 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n 01814 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n 01815 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n 01816 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n 01817 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n 01818 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n 01819 * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock 01820 * @param Periphs This parameter can be a combination of the following values: 01821 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01822 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01823 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01824 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01825 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01826 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01827 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 01828 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 01829 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 01830 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01831 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01832 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01833 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01834 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01835 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01836 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01837 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01838 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01839 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01840 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01841 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01842 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01843 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01844 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01845 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01846 * 01847 * (*) value not defined in all devices. 01848 * @retval None 01849 */ 01850 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 01851 { 01852 CLEAR_BIT(RCC->APB2ENR, Periphs); 01853 } 01854 01855 /** 01856 * @brief Force APB2 peripherals reset. 01857 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 01858 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 01859 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n 01860 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n 01861 * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n 01862 * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n 01863 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n 01864 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n 01865 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 01866 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n 01867 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n 01868 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n 01869 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n 01870 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n 01871 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n 01872 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n 01873 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n 01874 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n 01875 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n 01876 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n 01877 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n 01878 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset 01879 * @param Periphs This parameter can be a combination of the following values: 01880 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01881 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01882 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01883 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01884 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01885 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01886 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01887 * @arg @ref LL_APB2_GRP1_PERIPH_ADC 01888 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01889 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01890 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01891 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01892 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01893 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01894 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01895 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01896 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01897 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01898 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01899 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01900 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01901 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01902 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01903 * 01904 * (*) value not defined in all devices. 01905 * @retval None 01906 */ 01907 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 01908 { 01909 SET_BIT(RCC->APB2RSTR, Periphs); 01910 } 01911 01912 /** 01913 * @brief Release APB2 peripherals reset. 01914 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 01915 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 01916 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n 01917 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n 01918 * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n 01919 * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n 01920 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n 01921 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n 01922 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 01923 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n 01924 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n 01925 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n 01926 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n 01927 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n 01928 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n 01929 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n 01930 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n 01931 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n 01932 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n 01933 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n 01934 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n 01935 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset 01936 * @param Periphs This parameter can be a combination of the following values: 01937 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01938 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01939 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01940 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01941 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 01942 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 01943 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 01944 * @arg @ref LL_APB2_GRP1_PERIPH_ADC 01945 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 01946 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01947 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 01948 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01949 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 01950 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 01951 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 01952 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 01953 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 01954 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 01955 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 01956 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01957 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01958 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01959 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01960 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 01961 * 01962 * (*) value not defined in all devices. 01963 * @retval None 01964 */ 01965 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 01966 { 01967 CLEAR_BIT(RCC->APB2RSTR, Periphs); 01968 } 01969 01970 /** 01971 * @brief Enable APB2 peripheral clocks in low-power mode 01972 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01973 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n 01974 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01975 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n 01976 * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n 01977 * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n 01978 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01979 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n 01980 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n 01981 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n 01982 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01983 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n 01984 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n 01985 * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n 01986 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n 01987 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n 01988 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n 01989 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n 01990 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n 01991 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01992 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n 01993 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n 01994 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n 01995 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n 01996 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n 01997 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower 01998 * @param Periphs This parameter can be a combination of the following values: 01999 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02000 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 02001 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02002 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 02003 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02004 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 02005 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 02006 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 02007 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 02008 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 02009 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02010 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 02011 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 02012 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 02013 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 02014 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 02015 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 02016 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 02017 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 02018 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 02019 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02020 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 02021 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 02022 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 02023 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 02024 * 02025 * (*) value not defined in all devices. 02026 * @retval None 02027 */ 02028 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) 02029 { 02030 __IO uint32_t tmpreg; 02031 SET_BIT(RCC->APB2LPENR, Periphs); 02032 /* Delay after an RCC peripheral clock enabling */ 02033 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); 02034 (void)tmpreg; 02035 } 02036 02037 /** 02038 * @brief Disable APB2 peripheral clocks in low-power mode 02039 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02040 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n 02041 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02042 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n 02043 * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n 02044 * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n 02045 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02046 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n 02047 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n 02048 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n 02049 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02050 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n 02051 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n 02052 * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n 02053 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n 02054 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n 02055 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n 02056 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n 02057 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n 02058 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02059 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n 02060 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n 02061 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n 02062 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n 02063 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n 02064 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower 02065 * @param Periphs This parameter can be a combination of the following values: 02066 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 02067 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 02068 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 02069 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) 02070 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 02071 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) 02072 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 02073 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 02074 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 02075 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) 02076 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 02077 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) 02078 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 02079 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) 02080 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 02081 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 02082 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 02083 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) 02084 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) 02085 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) 02086 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 02087 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 02088 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 02089 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 02090 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) 02091 * 02092 * (*) value not defined in all devices. 02093 * @retval None 02094 */ 02095 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) 02096 { 02097 CLEAR_BIT(RCC->APB2LPENR, Periphs); 02098 } 02099 02100 /** 02101 * @} 02102 */ 02103 02104 /** 02105 * @} 02106 */ 02107 02108 /** 02109 * @} 02110 */ 02111 02112 #endif /* defined(RCC) */ 02113 02114 /** 02115 * @} 02116 */ 02117 02118 #ifdef __cplusplus 02119 } 02120 #endif 02121 02122 #endif /* __STM32F4xx_LL_BUS_H */ 02123 02124 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1