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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_tim.h 00004 * @author MCD Application Team 00005 * @brief Header file of TIM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_HAL_TIM_H 00038 #define __STM32F4xx_HAL_TIM_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx_hal_def.h" 00046 00047 /** @addtogroup STM32F4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup TIM 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup TIM_Exported_Types TIM Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief TIM Time base Configuration Structure definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00066 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ 00067 00068 uint32_t CounterMode; /*!< Specifies the counter mode. 00069 This parameter can be a value of @ref TIM_Counter_Mode */ 00070 00071 uint32_t Period; /*!< Specifies the period value to be loaded into the active 00072 Auto-Reload Register at the next update event. 00073 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFF. */ 00074 00075 uint32_t ClockDivision; /*!< Specifies the clock division. 00076 This parameter can be a value of @ref TIM_ClockDivision */ 00077 00078 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00079 reaches zero, an update event is generated and counting restarts 00080 from the RCR value (N). 00081 This means in PWM mode that (N+1) corresponds to: 00082 - the number of PWM periods in edge-aligned mode 00083 - the number of half PWM period in center-aligned mode 00084 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00085 @note This parameter is valid only for TIM1 and TIM8. */ 00086 } TIM_Base_InitTypeDef; 00087 00088 /** 00089 * @brief TIM Output Compare Configuration Structure definition 00090 */ 00091 00092 typedef struct 00093 { 00094 uint32_t OCMode; /*!< Specifies the TIM mode. 00095 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00096 00097 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00098 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ 00099 00100 uint32_t OCPolarity; /*!< Specifies the output polarity. 00101 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00102 00103 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00104 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00105 @note This parameter is valid only for TIM1 and TIM8. */ 00106 00107 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 00108 This parameter can be a value of @ref TIM_Output_Fast_State 00109 @note This parameter is valid only in PWM1 and PWM2 mode. */ 00110 00111 00112 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00113 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00114 @note This parameter is valid only for TIM1 and TIM8. */ 00115 00116 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00117 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00118 @note This parameter is valid only for TIM1 and TIM8. */ 00119 } TIM_OC_InitTypeDef; 00120 00121 /** 00122 * @brief TIM One Pulse Mode Configuration Structure definition 00123 */ 00124 typedef struct 00125 { 00126 uint32_t OCMode; /*!< Specifies the TIM mode. 00127 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 00128 00129 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 00130 This parameter can be a number between Min_Data = 0x0000U and Max_Data = 0xFFFFU */ 00131 00132 uint32_t OCPolarity; /*!< Specifies the output polarity. 00133 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 00134 00135 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00136 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 00137 @note This parameter is valid only for TIM1 and TIM8. */ 00138 00139 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00140 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 00141 @note This parameter is valid only for TIM1 and TIM8. */ 00142 00143 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00144 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 00145 @note This parameter is valid only for TIM1 and TIM8. */ 00146 00147 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00148 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00149 00150 uint32_t ICSelection; /*!< Specifies the input. 00151 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00152 00153 uint32_t ICFilter; /*!< Specifies the input capture filter. 00154 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00155 } TIM_OnePulse_InitTypeDef; 00156 00157 00158 /** 00159 * @brief TIM Input Capture Configuration Structure definition 00160 */ 00161 00162 typedef struct 00163 { 00164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00166 00167 uint32_t ICSelection; /*!< Specifies the input. 00168 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00169 00170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00172 00173 uint32_t ICFilter; /*!< Specifies the input capture filter. 00174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00175 } TIM_IC_InitTypeDef; 00176 00177 /** 00178 * @brief TIM Encoder Configuration Structure definition 00179 */ 00180 00181 typedef struct 00182 { 00183 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 00184 This parameter can be a value of @ref TIM_Encoder_Mode */ 00185 00186 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 00187 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00188 00189 uint32_t IC1Selection; /*!< Specifies the input. 00190 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00191 00192 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 00193 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00194 00195 uint32_t IC1Filter; /*!< Specifies the input capture filter. 00196 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00197 00198 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 00199 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 00200 00201 uint32_t IC2Selection; /*!< Specifies the input. 00202 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 00203 00204 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 00205 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 00206 00207 uint32_t IC2Filter; /*!< Specifies the input capture filter. 00208 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00209 } TIM_Encoder_InitTypeDef; 00210 00211 /** 00212 * @brief Clock Configuration Handle Structure definition 00213 */ 00214 typedef struct 00215 { 00216 uint32_t ClockSource; /*!< TIM clock sources. 00217 This parameter can be a value of @ref TIM_Clock_Source */ 00218 uint32_t ClockPolarity; /*!< TIM clock polarity. 00219 This parameter can be a value of @ref TIM_Clock_Polarity */ 00220 uint32_t ClockPrescaler; /*!< TIM clock prescaler. 00221 This parameter can be a value of @ref TIM_Clock_Prescaler */ 00222 uint32_t ClockFilter; /*!< TIM clock filter. 00223 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00224 }TIM_ClockConfigTypeDef; 00225 00226 /** 00227 * @brief Clear Input Configuration Handle Structure definition 00228 */ 00229 typedef struct 00230 { 00231 uint32_t ClearInputState; /*!< TIM clear Input state. 00232 This parameter can be ENABLE or DISABLE */ 00233 uint32_t ClearInputSource; /*!< TIM clear Input sources. 00234 This parameter can be a value of @ref TIM_ClearInput_Source */ 00235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. 00236 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 00237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. 00238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */ 00239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter. 00240 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00241 }TIM_ClearInputConfigTypeDef; 00242 00243 /** 00244 * @brief TIM Slave configuration Structure definition 00245 */ 00246 typedef struct { 00247 uint32_t SlaveMode; /*!< Slave mode selection 00248 This parameter can be a value of @ref TIM_Slave_Mode */ 00249 uint32_t InputTrigger; /*!< Input Trigger source 00250 This parameter can be a value of @ref TIM_Trigger_Selection */ 00251 uint32_t TriggerPolarity; /*!< Input Trigger polarity 00252 This parameter can be a value of @ref TIM_Trigger_Polarity */ 00253 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 00254 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 00255 uint32_t TriggerFilter; /*!< Input trigger filter 00256 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 00257 00258 }TIM_SlaveConfigTypeDef; 00259 00260 /** 00261 * @brief HAL State structures definition 00262 */ 00263 typedef enum 00264 { 00265 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 00266 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00267 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00268 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00269 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 00270 }HAL_TIM_StateTypeDef; 00271 00272 /** 00273 * @brief HAL Active channel structures definition 00274 */ 00275 typedef enum 00276 { 00277 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 00278 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 00279 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 00280 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 00281 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 00282 }HAL_TIM_ActiveChannel; 00283 00284 /** 00285 * @brief TIM Time Base Handle Structure definition 00286 */ 00287 typedef struct 00288 { 00289 TIM_TypeDef *Instance; /*!< Register base address */ 00290 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 00291 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 00292 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 00293 This array is accessed by a @ref DMA_Handle_index */ 00294 HAL_LockTypeDef Lock; /*!< Locking object */ 00295 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 00296 }TIM_HandleTypeDef; 00297 /** 00298 * @} 00299 */ 00300 00301 /* Exported constants --------------------------------------------------------*/ 00302 /** @defgroup TIM_Exported_Constants TIM Exported Constants 00303 * @{ 00304 */ 00305 00306 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity 00307 * @{ 00308 */ 00309 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 00310 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ 00311 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 00317 * @{ 00318 */ 00319 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ 00320 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 00321 /** 00322 * @} 00323 */ 00324 00325 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 00326 * @{ 00327 */ 00328 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 00329 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ 00330 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ 00331 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ 00332 /** 00333 * @} 00334 */ 00335 00336 /** @defgroup TIM_Counter_Mode TIM Counter Mode 00337 * @{ 00338 */ 00339 #define TIM_COUNTERMODE_UP 0x00000000U 00340 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR 00341 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 00342 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 00343 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup TIM_ClockDivision TIM Clock Division 00349 * @{ 00350 */ 00351 #define TIM_CLOCKDIVISION_DIV1 0x00000000U 00352 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) 00353 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes 00359 * @{ 00360 */ 00361 #define TIM_OCMODE_TIMING 0x00000000U 00362 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) 00363 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) 00364 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) 00365 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) 00366 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) 00367 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) 00368 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) 00369 00370 /** 00371 * @} 00372 */ 00373 00374 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 00375 * @{ 00376 */ 00377 #define TIM_OCFAST_DISABLE 0x00000000U 00378 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) 00379 /** 00380 * @} 00381 */ 00382 00383 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 00384 * @{ 00385 */ 00386 #define TIM_OCPOLARITY_HIGH 0x00000000U 00387 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) 00388 /** 00389 * @} 00390 */ 00391 00392 /** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity 00393 * @{ 00394 */ 00395 #define TIM_OCNPOLARITY_HIGH 0x00000000U 00396 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) 00397 /** 00398 * @} 00399 */ 00400 00401 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 00402 * @{ 00403 */ 00404 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) 00405 #define TIM_OCIDLESTATE_RESET 0x00000000U 00406 /** 00407 * @} 00408 */ 00409 00410 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State 00411 * @{ 00412 */ 00413 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) 00414 #define TIM_OCNIDLESTATE_RESET 0x00000000U 00415 /** 00416 * @} 00417 */ 00418 00419 /** @defgroup TIM_Channel TIM Channel 00420 * @{ 00421 */ 00422 #define TIM_CHANNEL_1 0x00000000U 00423 #define TIM_CHANNEL_2 0x00000004U 00424 #define TIM_CHANNEL_3 0x00000008U 00425 #define TIM_CHANNEL_4 0x0000000CU 00426 #define TIM_CHANNEL_ALL 0x00000018U 00427 00428 /** 00429 * @} 00430 */ 00431 00432 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 00433 * @{ 00434 */ 00435 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING 00436 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING 00437 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE 00438 /** 00439 * @} 00440 */ 00441 00442 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 00443 * @{ 00444 */ 00445 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be 00446 connected to IC1, IC2, IC3 or IC4, respectively */ 00447 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be 00448 connected to IC2, IC1, IC4 or IC3, respectively */ 00449 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 00450 00451 /** 00452 * @} 00453 */ 00454 00455 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 00456 * @{ 00457 */ 00458 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 00459 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ 00460 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ 00461 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ 00462 /** 00463 * @} 00464 */ 00465 00466 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 00467 * @{ 00468 */ 00469 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) 00470 #define TIM_OPMODE_REPETITIVE 0x00000000U 00471 /** 00472 * @} 00473 */ 00474 00475 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 00476 * @{ 00477 */ 00478 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) 00479 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) 00480 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) 00481 00482 /** 00483 * @} 00484 */ 00485 00486 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition 00487 * @{ 00488 */ 00489 #define TIM_IT_UPDATE (TIM_DIER_UIE) 00490 #define TIM_IT_CC1 (TIM_DIER_CC1IE) 00491 #define TIM_IT_CC2 (TIM_DIER_CC2IE) 00492 #define TIM_IT_CC3 (TIM_DIER_CC3IE) 00493 #define TIM_IT_CC4 (TIM_DIER_CC4IE) 00494 #define TIM_IT_COM (TIM_DIER_COMIE) 00495 #define TIM_IT_TRIGGER (TIM_DIER_TIE) 00496 #define TIM_IT_BREAK (TIM_DIER_BIE) 00497 /** 00498 * @} 00499 */ 00500 00501 /** @defgroup TIM_Commutation_Source TIM Commutation Source 00502 * @{ 00503 */ 00504 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) 00505 #define TIM_COMMUTATION_SOFTWARE 0x00000000U 00506 /** 00507 * @} 00508 */ 00509 00510 /** @defgroup TIM_DMA_sources TIM DMA sources 00511 * @{ 00512 */ 00513 #define TIM_DMA_UPDATE (TIM_DIER_UDE) 00514 #define TIM_DMA_CC1 (TIM_DIER_CC1DE) 00515 #define TIM_DMA_CC2 (TIM_DIER_CC2DE) 00516 #define TIM_DMA_CC3 (TIM_DIER_CC3DE) 00517 #define TIM_DMA_CC4 (TIM_DIER_CC4DE) 00518 #define TIM_DMA_COM (TIM_DIER_COMDE) 00519 #define TIM_DMA_TRIGGER (TIM_DIER_TDE) 00520 /** 00521 * @} 00522 */ 00523 00524 /** @defgroup TIM_Event_Source TIM Event Source 00525 * @{ 00526 */ 00527 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG 00528 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G 00529 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G 00530 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G 00531 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G 00532 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG 00533 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG 00534 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG 00535 00536 /** 00537 * @} 00538 */ 00539 00540 /** @defgroup TIM_Flag_definition TIM Flag definition 00541 * @{ 00542 */ 00543 #define TIM_FLAG_UPDATE (TIM_SR_UIF) 00544 #define TIM_FLAG_CC1 (TIM_SR_CC1IF) 00545 #define TIM_FLAG_CC2 (TIM_SR_CC2IF) 00546 #define TIM_FLAG_CC3 (TIM_SR_CC3IF) 00547 #define TIM_FLAG_CC4 (TIM_SR_CC4IF) 00548 #define TIM_FLAG_COM (TIM_SR_COMIF) 00549 #define TIM_FLAG_TRIGGER (TIM_SR_TIF) 00550 #define TIM_FLAG_BREAK (TIM_SR_BIF) 00551 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) 00552 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) 00553 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) 00554 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) 00555 /** 00556 * @} 00557 */ 00558 00559 /** @defgroup TIM_Clock_Source TIM Clock Source 00560 * @{ 00561 */ 00562 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) 00563 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) 00564 #define TIM_CLOCKSOURCE_ITR0 0x00000000U 00565 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) 00566 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) 00567 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) 00568 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) 00569 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) 00570 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) 00571 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) 00572 /** 00573 * @} 00574 */ 00575 00576 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 00577 * @{ 00578 */ 00579 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 00580 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 00581 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 00582 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 00583 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 00584 /** 00585 * @} 00586 */ 00587 00588 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 00589 * @{ 00590 */ 00591 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00592 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 00593 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 00594 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 00595 /** 00596 * @} 00597 */ 00598 00599 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 00600 * @{ 00601 */ 00602 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U 00603 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U 00604 /** 00605 * @} 00606 */ 00607 00608 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 00609 * @{ 00610 */ 00611 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 00612 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 00613 /** 00614 * @} 00615 */ 00616 00617 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 00618 * @{ 00619 */ 00620 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00621 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 00622 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 00623 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 00624 /** 00625 * @} 00626 */ 00627 00628 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 00629 * @{ 00630 */ 00631 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) 00632 #define TIM_OSSR_DISABLE 0x00000000U 00633 /** 00634 * @} 00635 */ 00636 00637 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 00638 * @{ 00639 */ 00640 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) 00641 #define TIM_OSSI_DISABLE 0x00000000U 00642 /** 00643 * @} 00644 */ 00645 00646 /** @defgroup TIM_Lock_level TIM Lock level 00647 * @{ 00648 */ 00649 #define TIM_LOCKLEVEL_OFF 0x00000000U 00650 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) 00651 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) 00652 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) 00653 /** 00654 * @} 00655 */ 00656 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State 00657 * @{ 00658 */ 00659 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) 00660 #define TIM_BREAK_DISABLE 0x00000000U 00661 /** 00662 * @} 00663 */ 00664 00665 /** @defgroup TIM_Break_Polarity TIM Break Polarity 00666 * @{ 00667 */ 00668 #define TIM_BREAKPOLARITY_LOW 0x00000000U 00669 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) 00670 /** 00671 * @} 00672 */ 00673 00674 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State 00675 * @{ 00676 */ 00677 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) 00678 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U 00679 /** 00680 * @} 00681 */ 00682 00683 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 00684 * @{ 00685 */ 00686 #define TIM_TRGO_RESET 0x00000000U 00687 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) 00688 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) 00689 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 00690 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) 00691 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) 00692 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) 00693 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) 00694 /** 00695 * @} 00696 */ 00697 00698 /** @defgroup TIM_Slave_Mode TIM Slave Mode 00699 * @{ 00700 */ 00701 #define TIM_SLAVEMODE_DISABLE 0x00000000U 00702 #define TIM_SLAVEMODE_RESET 0x00000004U 00703 #define TIM_SLAVEMODE_GATED 0x00000005U 00704 #define TIM_SLAVEMODE_TRIGGER 0x00000006U 00705 #define TIM_SLAVEMODE_EXTERNAL1 0x00000007U 00706 /** 00707 * @} 00708 */ 00709 00710 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode 00711 * @{ 00712 */ 00713 #define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U 00714 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U 00715 /** 00716 * @} 00717 */ 00718 00719 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 00720 * @{ 00721 */ 00722 #define TIM_TS_ITR0 0x00000000U 00723 #define TIM_TS_ITR1 0x00000010U 00724 #define TIM_TS_ITR2 0x00000020U 00725 #define TIM_TS_ITR3 0x00000030U 00726 #define TIM_TS_TI1F_ED 0x00000040U 00727 #define TIM_TS_TI1FP1 0x00000050U 00728 #define TIM_TS_TI2FP2 0x00000060U 00729 #define TIM_TS_ETRF 0x00000070U 00730 #define TIM_TS_NONE 0x0000FFFFU 00731 /** 00732 * @} 00733 */ 00734 00735 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 00736 * @{ 00737 */ 00738 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 00739 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 00740 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00741 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00742 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 00743 /** 00744 * @} 00745 */ 00746 00747 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 00748 * @{ 00749 */ 00750 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 00751 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 00752 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 00753 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 00754 /** 00755 * @} 00756 */ 00757 00758 00759 /** @defgroup TIM_TI1_Selection TIM TI1 Selection 00760 * @{ 00761 */ 00762 #define TIM_TI1SELECTION_CH1 0x00000000U 00763 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) 00764 /** 00765 * @} 00766 */ 00767 00768 /** @defgroup TIM_DMA_Base_address TIM DMA Base address 00769 * @{ 00770 */ 00771 #define TIM_DMABASE_CR1 0x00000000U 00772 #define TIM_DMABASE_CR2 0x00000001U 00773 #define TIM_DMABASE_SMCR 0x00000002U 00774 #define TIM_DMABASE_DIER 0x00000003U 00775 #define TIM_DMABASE_SR 0x00000004U 00776 #define TIM_DMABASE_EGR 0x00000005U 00777 #define TIM_DMABASE_CCMR1 0x00000006U 00778 #define TIM_DMABASE_CCMR2 0x00000007U 00779 #define TIM_DMABASE_CCER 0x00000008U 00780 #define TIM_DMABASE_CNT 0x00000009U 00781 #define TIM_DMABASE_PSC 0x0000000AU 00782 #define TIM_DMABASE_ARR 0x0000000BU 00783 #define TIM_DMABASE_RCR 0x0000000CU 00784 #define TIM_DMABASE_CCR1 0x0000000DU 00785 #define TIM_DMABASE_CCR2 0x0000000EU 00786 #define TIM_DMABASE_CCR3 0x0000000FU 00787 #define TIM_DMABASE_CCR4 0x00000010U 00788 #define TIM_DMABASE_BDTR 0x00000011U 00789 #define TIM_DMABASE_DCR 0x00000012U 00790 #define TIM_DMABASE_OR 0x00000013U 00791 /** 00792 * @} 00793 */ 00794 00795 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 00796 * @{ 00797 */ 00798 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U 00799 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U 00800 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U 00801 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U 00802 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U 00803 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U 00804 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U 00805 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U 00806 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U 00807 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U 00808 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U 00809 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U 00810 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U 00811 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U 00812 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U 00813 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U 00814 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U 00815 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U 00816 /** 00817 * @} 00818 */ 00819 00820 /** @defgroup DMA_Handle_index DMA Handle index 00821 * @{ 00822 */ 00823 #define TIM_DMA_ID_UPDATE ((uint16_t)0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 00824 #define TIM_DMA_ID_CC1 ((uint16_t)0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 00825 #define TIM_DMA_ID_CC2 ((uint16_t)0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 00826 #define TIM_DMA_ID_CC3 ((uint16_t)0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 00827 #define TIM_DMA_ID_CC4 ((uint16_t)0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 00828 #define TIM_DMA_ID_COMMUTATION ((uint16_t)0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 00829 #define TIM_DMA_ID_TRIGGER ((uint16_t)0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 00830 /** 00831 * @} 00832 */ 00833 00834 /** @defgroup Channel_CC_State Channel CC State 00835 * @{ 00836 */ 00837 #define TIM_CCx_ENABLE 0x00000001U 00838 #define TIM_CCx_DISABLE 0x00000000U 00839 #define TIM_CCxN_ENABLE 0x00000004U 00840 #define TIM_CCxN_DISABLE 0x00000000U 00841 /** 00842 * @} 00843 */ 00844 00845 /** 00846 * @} 00847 */ 00848 00849 /* Exported macro ------------------------------------------------------------*/ 00850 /** @defgroup TIM_Exported_Macros TIM Exported Macros 00851 * @{ 00852 */ 00853 /** @brief Reset TIM handle state 00854 * @param __HANDLE__ TIM handle 00855 * @retval None 00856 */ 00857 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 00858 00859 /** 00860 * @brief Enable the TIM peripheral. 00861 * @param __HANDLE__ TIM handle 00862 * @retval None 00863 */ 00864 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 00865 00866 /** 00867 * @brief Enable the TIM main Output. 00868 * @param __HANDLE__ TIM handle 00869 * @retval None 00870 */ 00871 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 00872 00873 00874 /** 00875 * @brief Disable the TIM peripheral. 00876 * @param __HANDLE__ TIM handle 00877 * @retval None 00878 */ 00879 #define __HAL_TIM_DISABLE(__HANDLE__) \ 00880 do { \ 00881 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ 00882 { \ 00883 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ 00884 { \ 00885 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 00886 } \ 00887 } \ 00888 } while(0U) 00889 00890 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN 00891 channels have been disabled */ 00892 /** 00893 * @brief Disable the TIM main Output. 00894 * @param __HANDLE__ TIM handle 00895 * @retval None 00896 */ 00897 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 00898 do { \ 00899 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ 00900 { \ 00901 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ 00902 { \ 00903 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 00904 } \ 00905 } \ 00906 } while(0U) 00907 00908 /** 00909 * @brief Disable the TIM main Output. 00910 * @param __HANDLE__ TIM handle 00911 * @retval None 00912 * @note The Main Output Enable of a timer instance is disabled unconditionally 00913 */ 00914 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 00915 00916 /** @brief Enable the specified TIM interrupt. 00917 * @param __HANDLE__ specifies the TIM Handle. 00918 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 00919 * This parameter can be one of the following values: 00920 * @arg TIM_IT_UPDATE: Update interrupt 00921 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 00922 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 00923 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 00924 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 00925 * @arg TIM_IT_COM: Commutation interrupt 00926 * @arg TIM_IT_TRIGGER: Trigger interrupt 00927 * @arg TIM_IT_BREAK: Break interrupt 00928 * @retval None 00929 */ 00930 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 00931 00932 00933 /** @brief Disable the specified TIM interrupt. 00934 * @param __HANDLE__ specifies the TIM Handle. 00935 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 00936 * This parameter can be one of the following values: 00937 * @arg TIM_IT_UPDATE: Update interrupt 00938 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 00939 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 00940 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 00941 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 00942 * @arg TIM_IT_COM: Commutation interrupt 00943 * @arg TIM_IT_TRIGGER: Trigger interrupt 00944 * @arg TIM_IT_BREAK: Break interrupt 00945 * @retval None 00946 */ 00947 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 00948 00949 /** @brief Enable the specified DMA request. 00950 * @param __HANDLE__ specifies the TIM Handle. 00951 * @param __DMA__ specifies the TIM DMA request to enable. 00952 * This parameter can be one of the following values: 00953 * @arg TIM_DMA_UPDATE: Update DMA request 00954 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 00955 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 00956 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 00957 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 00958 * @arg TIM_DMA_COM: Commutation DMA request 00959 * @arg TIM_DMA_TRIGGER: Trigger DMA request 00960 * @retval None 00961 */ 00962 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 00963 00964 /** @brief Disable the specified DMA request. 00965 * @param __HANDLE__ specifies the TIM Handle. 00966 * @param __DMA__ specifies the TIM DMA request to disable. 00967 * This parameter can be one of the following values: 00968 * @arg TIM_DMA_UPDATE: Update DMA request 00969 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 00970 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 00971 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 00972 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 00973 * @arg TIM_DMA_COM: Commutation DMA request 00974 * @arg TIM_DMA_TRIGGER: Trigger DMA request 00975 * @retval None 00976 */ 00977 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 00978 00979 /** @brief Check whether the specified TIM interrupt flag is set or not. 00980 * @param __HANDLE__ specifies the TIM Handle. 00981 * @param __FLAG__ specifies the TIM interrupt flag to check. 00982 * This parameter can be one of the following values: 00983 * @arg TIM_FLAG_UPDATE: Update interrupt flag 00984 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 00985 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 00986 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 00987 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 00988 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 00989 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 00990 * @arg TIM_FLAG_COM: Commutation interrupt flag 00991 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 00992 * @arg TIM_FLAG_BREAK: Break interrupt flag 00993 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 00994 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 00995 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 00996 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 00997 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 00998 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 00999 * @retval The new state of __FLAG__ (TRUE or FALSE). 01000 */ 01001 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 01002 01003 /** @brief Clear the specified TIM interrupt flag. 01004 * @param __HANDLE__ specifies the TIM Handle. 01005 * @param __FLAG__ specifies the TIM interrupt flag to clear. 01006 * This parameter can be one of the following values: 01007 * @arg TIM_FLAG_UPDATE: Update interrupt flag 01008 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 01009 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 01010 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 01011 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 01012 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 01013 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 01014 * @arg TIM_FLAG_COM: Commutation interrupt flag 01015 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 01016 * @arg TIM_FLAG_BREAK: Break interrupt flag 01017 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 01018 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 01019 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 01020 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 01021 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 01022 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 01023 * @retval The new state of __FLAG__ (TRUE or FALSE). 01024 */ 01025 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 01026 01027 /** 01028 * @brief Check whether the specified TIM interrupt source is enabled or not. 01029 * @param __HANDLE__ TIM handle 01030 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 01031 * This parameter can be one of the following values: 01032 * @arg TIM_IT_UPDATE: Update interrupt 01033 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01034 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01035 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01036 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01037 * @arg TIM_IT_COM: Commutation interrupt 01038 * @arg TIM_IT_TRIGGER: Trigger interrupt 01039 * @arg TIM_IT_BREAK: Break interrupt 01040 * @retval The state of TIM_IT (SET or RESET). 01041 */ 01042 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 01043 01044 /** @brief Clear the TIM interrupt pending bits. 01045 * @param __HANDLE__ TIM handle 01046 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 01047 * This parameter can be one of the following values: 01048 * @arg TIM_IT_UPDATE: Update interrupt 01049 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 01050 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 01051 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 01052 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 01053 * @arg TIM_IT_COM: Commutation interrupt 01054 * @arg TIM_IT_TRIGGER: Trigger interrupt 01055 * @arg TIM_IT_BREAK: Break interrupt 01056 * @retval None 01057 */ 01058 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 01059 01060 /** 01061 * @brief Indicates whether or not the TIM Counter is used as downcounter. 01062 * @param __HANDLE__ TIM handle. 01063 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 01064 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 01065 mode. 01066 */ 01067 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 01068 01069 /** 01070 * @brief Set the TIM Prescaler on runtime. 01071 * @param __HANDLE__ TIM handle. 01072 * @param __PRESC__ specifies the Prescaler new value. 01073 * @retval None 01074 */ 01075 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 01076 01077 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01078 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 01079 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 01080 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 01081 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 01082 01083 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 01084 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ 01085 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ 01086 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ 01087 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) 01088 01089 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01090 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 01091 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 01092 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 01093 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) 01094 01095 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 01096 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 01097 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 01098 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 01099 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) 01100 01101 /** 01102 * @brief Sets the TIM Capture Compare Register value on runtime without 01103 * calling another time ConfigChannel function. 01104 * @param __HANDLE__ TIM handle. 01105 * @param __CHANNEL__ TIM Channels to be configured. 01106 * This parameter can be one of the following values: 01107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01109 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01110 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01111 * @param __COMPARE__ specifies the Capture Compare register new value. 01112 * @retval None 01113 */ 01114 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 01115 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) 01116 01117 /** 01118 * @brief Gets the TIM Capture Compare Register value on runtime. 01119 * @param __HANDLE__ TIM handle. 01120 * @param __CHANNEL__ TIM Channel associated with the capture compare register 01121 * This parameter can be one of the following values: 01122 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 01123 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 01124 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 01125 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 01126 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 01127 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 01128 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 01129 */ 01130 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 01131 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) 01132 01133 /** 01134 * @brief Sets the TIM Counter Register value on runtime. 01135 * @param __HANDLE__ TIM handle. 01136 * @param __COUNTER__ specifies the Counter register new value. 01137 * @retval None 01138 */ 01139 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 01140 01141 /** 01142 * @brief Gets the TIM Counter Register value on runtime. 01143 * @param __HANDLE__ TIM handle. 01144 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 01145 */ 01146 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 01147 01148 /** 01149 * @brief Sets the TIM Autoreload Register value on runtime without calling 01150 * another time any Init function. 01151 * @param __HANDLE__ TIM handle. 01152 * @param __AUTORELOAD__ specifies the Counter register new value. 01153 * @retval None 01154 */ 01155 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 01156 do{ \ 01157 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 01158 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 01159 } while(0U) 01160 /** 01161 * @brief Gets the TIM Autoreload Register value on runtime. 01162 * @param __HANDLE__ TIM handle. 01163 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 01164 */ 01165 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 01166 01167 /** 01168 * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function. 01169 * @param __HANDLE__ TIM handle. 01170 * @param __CKD__ specifies the clock division value. 01171 * This parameter can be one of the following value: 01172 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 01173 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 01174 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 01175 * @retval None 01176 */ 01177 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 01178 do{ \ 01179 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ 01180 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 01181 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 01182 } while(0U) 01183 /** 01184 * @brief Gets the TIM Clock Division value on runtime. 01185 * @param __HANDLE__ TIM handle. 01186 * @retval The clock division can be one of the following values: 01187 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 01188 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 01189 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 01190 */ 01191 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 01192 01193 /** 01194 * @brief Sets the TIM Input Capture prescaler on runtime without calling 01195 * another time HAL_TIM_IC_ConfigChannel() function. 01196 * @param __HANDLE__ TIM handle. 01197 * @param __CHANNEL__ TIM Channels to be configured. 01198 * This parameter can be one of the following values: 01199 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01200 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01201 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01202 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01203 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 01204 * This parameter can be one of the following values: 01205 * @arg TIM_ICPSC_DIV1: no prescaler 01206 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01207 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01208 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01209 * @retval None 01210 */ 01211 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 01212 do{ \ 01213 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 01214 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 01215 } while(0U) 01216 01217 /** 01218 * @brief Get the TIM Input Capture prescaler on runtime. 01219 * @param __HANDLE__ TIM handle. 01220 * @param __CHANNEL__ TIM Channels to be configured. 01221 * This parameter can be one of the following values: 01222 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 01223 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 01224 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 01225 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 01226 * @retval The input capture prescaler can be one of the following values: 01227 * @arg TIM_ICPSC_DIV1: no prescaler 01228 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 01229 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 01230 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 01231 */ 01232 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 01233 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 01234 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 01235 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 01236 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 01237 01238 /** 01239 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register 01240 * @param __HANDLE__ TIM handle. 01241 * @note When the USR bit of the TIMx_CR1 register is set, only counter 01242 * overflow/underflow generates an update interrupt or DMA request (if 01243 * enabled) 01244 * @retval None 01245 */ 01246 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ 01247 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) 01248 01249 /** 01250 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register 01251 * @param __HANDLE__ TIM handle. 01252 * @note When the USR bit of the TIMx_CR1 register is reset, any of the 01253 * following events generate an update interrupt or DMA request (if 01254 * enabled): 01255 * _ Counter overflow/underflow 01256 * _ Setting the UG bit 01257 * _ Update generation through the slave mode controller 01258 * @retval None 01259 */ 01260 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ 01261 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) 01262 01263 /** 01264 * @brief Sets the TIM Capture x input polarity on runtime. 01265 * @param __HANDLE__ TIM handle. 01266 * @param __CHANNEL__ TIM Channels to be configured. 01267 * This parameter can be one of the following values: 01268 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01269 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01270 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01271 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01272 * @param __POLARITY__ Polarity for TIx source 01273 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 01274 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 01275 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 01276 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. 01277 * @retval None 01278 */ 01279 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 01280 do{ \ 01281 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 01282 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 01283 }while(0U) 01284 /** 01285 * @} 01286 */ 01287 01288 /* Include TIM HAL Extension module */ 01289 #include "stm32f4xx_hal_tim_ex.h" 01290 01291 /* Exported functions --------------------------------------------------------*/ 01292 /** @addtogroup TIM_Exported_Functions 01293 * @{ 01294 */ 01295 01296 /** @addtogroup TIM_Exported_Functions_Group1 01297 * @{ 01298 */ 01299 01300 /* Time Base functions ********************************************************/ 01301 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 01302 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 01303 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 01304 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 01305 /* Blocking mode: Polling */ 01306 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 01307 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 01308 /* Non-Blocking mode: Interrupt */ 01309 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 01310 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 01311 /* Non-Blocking mode: DMA */ 01312 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 01313 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 01314 /** 01315 * @} 01316 */ 01317 01318 /** @addtogroup TIM_Exported_Functions_Group2 01319 * @{ 01320 */ 01321 /* Timer Output Compare functions **********************************************/ 01322 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 01323 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 01324 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 01325 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 01326 /* Blocking mode: Polling */ 01327 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01328 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01329 /* Non-Blocking mode: Interrupt */ 01330 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01331 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01332 /* Non-Blocking mode: DMA */ 01333 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01334 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01335 01336 /** 01337 * @} 01338 */ 01339 01340 /** @addtogroup TIM_Exported_Functions_Group3 01341 * @{ 01342 */ 01343 /* Timer PWM functions *********************************************************/ 01344 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 01345 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 01346 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 01347 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 01348 /* Blocking mode: Polling */ 01349 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01350 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01351 /* Non-Blocking mode: Interrupt */ 01352 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01353 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01354 /* Non-Blocking mode: DMA */ 01355 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01356 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01357 01358 /** 01359 * @} 01360 */ 01361 01362 /** @addtogroup TIM_Exported_Functions_Group4 01363 * @{ 01364 */ 01365 /* Timer Input Capture functions ***********************************************/ 01366 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 01367 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 01368 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 01369 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 01370 /* Blocking mode: Polling */ 01371 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01372 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01373 /* Non-Blocking mode: Interrupt */ 01374 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01375 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01376 /* Non-Blocking mode: DMA */ 01377 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 01378 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01379 01380 /** 01381 * @} 01382 */ 01383 01384 /** @addtogroup TIM_Exported_Functions_Group5 01385 * @{ 01386 */ 01387 /* Timer One Pulse functions ***************************************************/ 01388 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 01389 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 01390 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 01391 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 01392 /* Blocking mode: Polling */ 01393 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01394 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01395 01396 /* Non-Blocking mode: Interrupt */ 01397 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01398 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 01399 01400 /** 01401 * @} 01402 */ 01403 01404 /** @addtogroup TIM_Exported_Functions_Group6 01405 * @{ 01406 */ 01407 /* Timer Encoder functions *****************************************************/ 01408 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); 01409 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 01410 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 01411 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 01412 /* Blocking mode: Polling */ 01413 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 01414 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 01415 /* Non-Blocking mode: Interrupt */ 01416 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01417 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 01418 /* Non-Blocking mode: DMA */ 01419 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); 01420 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 01421 01422 /** 01423 * @} 01424 */ 01425 01426 /** @addtogroup TIM_Exported_Functions_Group7 01427 * @{ 01428 */ 01429 /* Interrupt Handler functions **********************************************/ 01430 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 01431 01432 /** 01433 * @} 01434 */ 01435 01436 /** @addtogroup TIM_Exported_Functions_Group8 01437 * @{ 01438 */ 01439 /* Control functions *********************************************************/ 01440 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); 01441 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); 01442 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); 01443 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); 01444 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); 01445 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); 01446 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 01447 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); 01448 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); 01449 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 01450 uint32_t *BurstBuffer, uint32_t BurstLength); 01451 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 01452 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ 01453 uint32_t *BurstBuffer, uint32_t BurstLength); 01454 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 01455 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 01456 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 01457 01458 /** 01459 * @} 01460 */ 01461 01462 /** @addtogroup TIM_Exported_Functions_Group9 01463 * @{ 01464 */ 01465 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 01466 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 01467 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 01468 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 01469 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 01470 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 01471 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 01472 01473 /** 01474 * @} 01475 */ 01476 01477 /** @addtogroup TIM_Exported_Functions_Group10 01478 * @{ 01479 */ 01480 /* Peripheral State functions **************************************************/ 01481 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 01482 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 01483 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 01484 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 01485 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 01486 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 01487 01488 /** 01489 * @} 01490 */ 01491 01492 /** 01493 * @} 01494 */ 01495 01496 /* Private macros ------------------------------------------------------------*/ 01497 /** @defgroup TIM_Private_Macros TIM Private Macros 01498 * @{ 01499 */ 01500 01501 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters 01502 * @{ 01503 */ 01504 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ 01505 ((MODE) == TIM_COUNTERMODE_DOWN) || \ 01506 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 01507 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 01508 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) 01509 01510 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ 01511 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ 01512 ((DIV) == TIM_CLOCKDIVISION_DIV4)) 01513 01514 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ 01515 ((MODE) == TIM_OCMODE_PWM2)) 01516 01517 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ 01518 ((MODE) == TIM_OCMODE_ACTIVE) || \ 01519 ((MODE) == TIM_OCMODE_INACTIVE) || \ 01520 ((MODE) == TIM_OCMODE_TOGGLE) || \ 01521 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ 01522 ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) 01523 01524 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ 01525 ((STATE) == TIM_OCFAST_ENABLE)) 01526 01527 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ 01528 ((POLARITY) == TIM_OCPOLARITY_LOW)) 01529 01530 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \ 01531 ((POLARITY) == TIM_OCNPOLARITY_LOW)) 01532 01533 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ 01534 ((STATE) == TIM_OCIDLESTATE_RESET)) 01535 01536 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ 01537 ((STATE) == TIM_OCNIDLESTATE_RESET)) 01538 01539 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ 01540 ((CHANNEL) == TIM_CHANNEL_2) || \ 01541 ((CHANNEL) == TIM_CHANNEL_3) || \ 01542 ((CHANNEL) == TIM_CHANNEL_4) || \ 01543 ((CHANNEL) == TIM_CHANNEL_ALL)) 01544 01545 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ 01546 ((CHANNEL) == TIM_CHANNEL_2)) 01547 01548 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ 01549 ((CHANNEL) == TIM_CHANNEL_2) || \ 01550 ((CHANNEL) == TIM_CHANNEL_3)) 01551 01552 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ 01553 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ 01554 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) 01555 01556 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ 01557 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ 01558 ((SELECTION) == TIM_ICSELECTION_TRC)) 01559 01560 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 01561 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 01562 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 01563 ((PRESCALER) == TIM_ICPSC_DIV8)) 01564 01565 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ 01566 ((MODE) == TIM_OPMODE_REPETITIVE)) 01567 01568 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) 01569 01570 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ 01571 ((MODE) == TIM_ENCODERMODE_TI2) || \ 01572 ((MODE) == TIM_ENCODERMODE_TI12)) 01573 01574 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) 01575 01576 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ 01577 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ 01578 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ 01579 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ 01580 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ 01581 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ 01582 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ 01583 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ 01584 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ 01585 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) 01586 01587 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ 01588 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 01589 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ 01590 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ 01591 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) 01592 01593 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ 01594 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ 01595 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ 01596 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) 01597 01598 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 01599 01600 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ 01601 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) 01602 01603 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 01604 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 01605 01606 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 01607 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 01608 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 01609 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) 01610 01611 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 01612 01613 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ 01614 ((STATE) == TIM_OSSR_DISABLE)) 01615 01616 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ 01617 ((STATE) == TIM_OSSI_DISABLE)) 01618 01619 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \ 01620 ((LEVEL) == TIM_LOCKLEVEL_1) || \ 01621 ((LEVEL) == TIM_LOCKLEVEL_2) || \ 01622 ((LEVEL) == TIM_LOCKLEVEL_3)) 01623 01624 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ 01625 ((STATE) == TIM_BREAK_DISABLE)) 01626 01627 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \ 01628 ((POLARITY) == TIM_BREAKPOLARITY_HIGH)) 01629 01630 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 01631 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE)) 01632 01633 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ 01634 ((SOURCE) == TIM_TRGO_ENABLE) || \ 01635 ((SOURCE) == TIM_TRGO_UPDATE) || \ 01636 ((SOURCE) == TIM_TRGO_OC1) || \ 01637 ((SOURCE) == TIM_TRGO_OC1REF) || \ 01638 ((SOURCE) == TIM_TRGO_OC2REF) || \ 01639 ((SOURCE) == TIM_TRGO_OC3REF) || \ 01640 ((SOURCE) == TIM_TRGO_OC4REF)) 01641 01642 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ 01643 ((MODE) == TIM_SLAVEMODE_GATED) || \ 01644 ((MODE) == TIM_SLAVEMODE_RESET) || \ 01645 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ 01646 ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) 01647 01648 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ 01649 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) 01650 01651 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 01652 ((SELECTION) == TIM_TS_ITR1) || \ 01653 ((SELECTION) == TIM_TS_ITR2) || \ 01654 ((SELECTION) == TIM_TS_ITR3) || \ 01655 ((SELECTION) == TIM_TS_TI1F_ED) || \ 01656 ((SELECTION) == TIM_TS_TI1FP1) || \ 01657 ((SELECTION) == TIM_TS_TI2FP2) || \ 01658 ((SELECTION) == TIM_TS_ETRF)) 01659 01660 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 01661 ((SELECTION) == TIM_TS_ITR1) || \ 01662 ((SELECTION) == TIM_TS_ITR2) || \ 01663 ((SELECTION) == TIM_TS_ITR3) || \ 01664 ((SELECTION) == TIM_TS_NONE)) 01665 01666 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 01667 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 01668 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ 01669 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ 01670 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 01671 01672 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ 01673 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ 01674 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ 01675 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) 01676 01677 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 01678 01679 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ 01680 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) 01681 01682 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \ 01683 ((BASE) == TIM_DMABASE_CR2) || \ 01684 ((BASE) == TIM_DMABASE_SMCR) || \ 01685 ((BASE) == TIM_DMABASE_DIER) || \ 01686 ((BASE) == TIM_DMABASE_SR) || \ 01687 ((BASE) == TIM_DMABASE_EGR) || \ 01688 ((BASE) == TIM_DMABASE_CCMR1) || \ 01689 ((BASE) == TIM_DMABASE_CCMR2) || \ 01690 ((BASE) == TIM_DMABASE_CCER) || \ 01691 ((BASE) == TIM_DMABASE_CNT) || \ 01692 ((BASE) == TIM_DMABASE_PSC) || \ 01693 ((BASE) == TIM_DMABASE_ARR) || \ 01694 ((BASE) == TIM_DMABASE_RCR) || \ 01695 ((BASE) == TIM_DMABASE_CCR1) || \ 01696 ((BASE) == TIM_DMABASE_CCR2) || \ 01697 ((BASE) == TIM_DMABASE_CCR3) || \ 01698 ((BASE) == TIM_DMABASE_CCR4) || \ 01699 ((BASE) == TIM_DMABASE_BDTR) || \ 01700 ((BASE) == TIM_DMABASE_DCR) || \ 01701 ((BASE) == TIM_DMABASE_OR)) 01702 01703 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 01704 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 01705 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 01706 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 01707 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 01708 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 01709 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 01710 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 01711 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 01712 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 01713 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 01714 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 01715 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 01716 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 01717 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 01718 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 01719 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 01720 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) 01721 01722 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) 01723 /** 01724 * @} 01725 */ 01726 01727 /** @defgroup TIM_Mask_Definitions TIM Mask Definition 01728 * @{ 01729 */ 01730 /* The counter of a timer instance is disabled only if all the CCx and CCxN 01731 channels have been disabled */ 01732 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 01733 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 01734 /** 01735 * @} 01736 */ 01737 01738 /** 01739 * @} 01740 */ 01741 01742 /* Private functions ---------------------------------------------------------*/ 01743 /** @defgroup TIM_Private_Functions TIM Private Functions 01744 * @{ 01745 */ 01746 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 01747 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 01748 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 01749 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 01750 void TIM_DMAError(DMA_HandleTypeDef *hdma); 01751 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 01752 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); 01753 /** 01754 * @} 01755 */ 01756 01757 /** 01758 * @} 01759 */ 01760 01761 /** 01762 * @} 01763 */ 01764 01765 #ifdef __cplusplus 01766 } 01767 #endif 01768 01769 #endif /* __STM32F4xx_HAL_TIM_H */ 01770 01771 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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