STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_sram.c 00004 * @author MCD Application Team 00005 * @brief SRAM HAL module driver. 00006 * This file provides a generic firmware to drive SRAM memories 00007 * mounted as external device. 00008 * 00009 @verbatim 00010 ============================================================================== 00011 ##### How to use this driver ##### 00012 ============================================================================== 00013 [..] 00014 This driver is a generic layered driver which contains a set of APIs used to 00015 control SRAM memories. It uses the FMC layer functions to interface 00016 with SRAM devices. 00017 The following sequence should be followed to configure the FMC/FSMC to interface 00018 with SRAM/PSRAM memories: 00019 00020 (#) Declare a SRAM_HandleTypeDef handle structure, for example: 00021 SRAM_HandleTypeDef hsram; and: 00022 00023 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed 00024 values of the structure member. 00025 00026 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined 00027 base register instance for NOR or SRAM device 00028 00029 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined 00030 base register instance for NOR or SRAM extended mode 00031 00032 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended 00033 mode timings; for example: 00034 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; 00035 and fill its fields with the allowed values of the structure member. 00036 00037 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function 00038 performs the following sequence: 00039 00040 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() 00041 (##) Control register configuration using the FMC NORSRAM interface function 00042 FMC_NORSRAM_Init() 00043 (##) Timing register configuration using the FMC NORSRAM interface function 00044 FMC_NORSRAM_Timing_Init() 00045 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function 00046 FMC_NORSRAM_Extended_Timing_Init() 00047 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() 00048 00049 (#) At this stage you can perform read/write accesses from/to the memory connected 00050 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the 00051 following APIs: 00052 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access 00053 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer 00054 00055 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ 00056 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation 00057 00058 (#) You can continuously monitor the SRAM device HAL state by calling the function 00059 HAL_SRAM_GetState() 00060 00061 @endverbatim 00062 ****************************************************************************** 00063 * @attention 00064 * 00065 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00066 * 00067 * Redistribution and use in source and binary forms, with or without modification, 00068 * are permitted provided that the following conditions are met: 00069 * 1. Redistributions of source code must retain the above copyright notice, 00070 * this list of conditions and the following disclaimer. 00071 * 2. Redistributions in binary form must reproduce the above copyright notice, 00072 * this list of conditions and the following disclaimer in the documentation 00073 * and/or other materials provided with the distribution. 00074 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00075 * may be used to endorse or promote products derived from this software 00076 * without specific prior written permission. 00077 * 00078 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00079 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00080 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00081 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00082 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00083 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00084 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00085 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00086 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00087 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00088 * 00089 ****************************************************************************** 00090 */ 00091 00092 /* Includes ------------------------------------------------------------------*/ 00093 #include "stm32f4xx_hal.h" 00094 00095 /** @addtogroup STM32F4xx_HAL_Driver 00096 * @{ 00097 */ 00098 00099 /** @defgroup SRAM SRAM 00100 * @brief SRAM driver modules 00101 * @{ 00102 */ 00103 #ifdef HAL_SRAM_MODULE_ENABLED 00104 00105 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ 00106 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 00107 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ 00108 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 00109 00110 /* Private typedef -----------------------------------------------------------*/ 00111 /* Private define ------------------------------------------------------------*/ 00112 /* Private macro -------------------------------------------------------------*/ 00113 /* Private variables ---------------------------------------------------------*/ 00114 /* Private functions ---------------------------------------------------------*/ 00115 00116 /* Exported functions --------------------------------------------------------*/ 00117 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions 00118 * @{ 00119 */ 00120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 00121 * @brief Initialization and Configuration functions 00122 * 00123 @verbatim 00124 ============================================================================== 00125 ##### SRAM Initialization and de_initialization functions ##### 00126 ============================================================================== 00127 [..] This section provides functions allowing to initialize/de-initialize 00128 the SRAM memory 00129 00130 @endverbatim 00131 * @{ 00132 */ 00133 00134 /** 00135 * @brief Performs the SRAM device initialization sequence 00136 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00137 * the configuration information for SRAM module. 00138 * @param Timing Pointer to SRAM control timing structure 00139 * @param ExtTiming Pointer to SRAM extended mode timing structure 00140 * @retval HAL status 00141 */ 00142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) 00143 { 00144 /* Check the SRAM handle parameter */ 00145 if(hsram == NULL) 00146 { 00147 return HAL_ERROR; 00148 } 00149 00150 if(hsram->State == HAL_SRAM_STATE_RESET) 00151 { 00152 /* Allocate lock resource and initialize it */ 00153 hsram->Lock = HAL_UNLOCKED; 00154 /* Initialize the low level hardware (MSP) */ 00155 HAL_SRAM_MspInit(hsram); 00156 } 00157 00158 /* Initialize SRAM control Interface */ 00159 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); 00160 00161 /* Initialize SRAM timing Interface */ 00162 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); 00163 00164 /* Initialize SRAM extended mode timing Interface */ 00165 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); 00166 00167 /* Enable the NORSRAM device */ 00168 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); 00169 00170 return HAL_OK; 00171 } 00172 00173 /** 00174 * @brief Performs the SRAM device De-initialization sequence. 00175 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00176 * the configuration information for SRAM module. 00177 * @retval HAL status 00178 */ 00179 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) 00180 { 00181 /* De-Initialize the low level hardware (MSP) */ 00182 HAL_SRAM_MspDeInit(hsram); 00183 00184 /* Configure the SRAM registers with their reset values */ 00185 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); 00186 00187 hsram->State = HAL_SRAM_STATE_RESET; 00188 00189 /* Release Lock */ 00190 __HAL_UNLOCK(hsram); 00191 00192 return HAL_OK; 00193 } 00194 00195 /** 00196 * @brief SRAM MSP Init. 00197 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00198 * the configuration information for SRAM module. 00199 * @retval None 00200 */ 00201 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) 00202 { 00203 /* Prevent unused argument(s) compilation warning */ 00204 UNUSED(hsram); 00205 /* NOTE : This function Should not be modified, when the callback is needed, 00206 the HAL_SRAM_MspInit could be implemented in the user file 00207 */ 00208 } 00209 00210 /** 00211 * @brief SRAM MSP DeInit. 00212 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00213 * the configuration information for SRAM module. 00214 * @retval None 00215 */ 00216 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) 00217 { 00218 /* Prevent unused argument(s) compilation warning */ 00219 UNUSED(hsram); 00220 /* NOTE : This function Should not be modified, when the callback is needed, 00221 the HAL_SRAM_MspDeInit could be implemented in the user file 00222 */ 00223 } 00224 00225 /** 00226 * @brief DMA transfer complete callback. 00227 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains 00228 * the configuration information for SRAM module. 00229 * @retval None 00230 */ 00231 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) 00232 { 00233 /* Prevent unused argument(s) compilation warning */ 00234 UNUSED(hdma); 00235 /* NOTE : This function Should not be modified, when the callback is needed, 00236 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file 00237 */ 00238 } 00239 00240 /** 00241 * @brief DMA transfer complete error callback. 00242 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains 00243 * the configuration information for SRAM module. 00244 * @retval None 00245 */ 00246 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) 00247 { 00248 /* Prevent unused argument(s) compilation warning */ 00249 UNUSED(hdma); 00250 /* NOTE : This function Should not be modified, when the callback is needed, 00251 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file 00252 */ 00253 } 00254 00255 /** 00256 * @} 00257 */ 00258 00259 /** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions 00260 * @brief Input Output and memory control functions 00261 * 00262 @verbatim 00263 ============================================================================== 00264 ##### SRAM Input and Output functions ##### 00265 ============================================================================== 00266 [..] 00267 This section provides functions allowing to use and control the SRAM memory 00268 00269 @endverbatim 00270 * @{ 00271 */ 00272 00273 /** 00274 * @brief Reads 8-bit buffer from SRAM memory. 00275 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00276 * the configuration information for SRAM module. 00277 * @param pAddress Pointer to read start address 00278 * @param pDstBuffer Pointer to destination buffer 00279 * @param BufferSize Size of the buffer to read from memory 00280 * @retval HAL status 00281 */ 00282 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) 00283 { 00284 __IO uint8_t * pSramAddress = (uint8_t *)pAddress; 00285 00286 /* Process Locked */ 00287 __HAL_LOCK(hsram); 00288 00289 /* Update the SRAM controller state */ 00290 hsram->State = HAL_SRAM_STATE_BUSY; 00291 00292 /* Read data from memory */ 00293 for(; BufferSize != 0U; BufferSize--) 00294 { 00295 *pDstBuffer = *(__IO uint8_t *)pSramAddress; 00296 pDstBuffer++; 00297 pSramAddress++; 00298 } 00299 00300 /* Update the SRAM controller state */ 00301 hsram->State = HAL_SRAM_STATE_READY; 00302 00303 /* Process unlocked */ 00304 __HAL_UNLOCK(hsram); 00305 00306 return HAL_OK; 00307 } 00308 00309 /** 00310 * @brief Writes 8-bit buffer to SRAM memory. 00311 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00312 * the configuration information for SRAM module. 00313 * @param pAddress Pointer to write start address 00314 * @param pSrcBuffer Pointer to source buffer to write 00315 * @param BufferSize Size of the buffer to write to memory 00316 * @retval HAL status 00317 */ 00318 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) 00319 { 00320 __IO uint8_t * pSramAddress = (uint8_t *)pAddress; 00321 00322 /* Check the SRAM controller state */ 00323 if(hsram->State == HAL_SRAM_STATE_PROTECTED) 00324 { 00325 return HAL_ERROR; 00326 } 00327 00328 /* Process Locked */ 00329 __HAL_LOCK(hsram); 00330 00331 /* Update the SRAM controller state */ 00332 hsram->State = HAL_SRAM_STATE_BUSY; 00333 00334 /* Write data to memory */ 00335 for(; BufferSize != 0U; BufferSize--) 00336 { 00337 *(__IO uint8_t *)pSramAddress = *pSrcBuffer; 00338 pSrcBuffer++; 00339 pSramAddress++; 00340 } 00341 00342 /* Update the SRAM controller state */ 00343 hsram->State = HAL_SRAM_STATE_READY; 00344 00345 /* Process unlocked */ 00346 __HAL_UNLOCK(hsram); 00347 00348 return HAL_OK; 00349 } 00350 00351 /** 00352 * @brief Reads 16-bit buffer from SRAM memory. 00353 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00354 * the configuration information for SRAM module. 00355 * @param pAddress Pointer to read start address 00356 * @param pDstBuffer Pointer to destination buffer 00357 * @param BufferSize Size of the buffer to read from memory 00358 * @retval HAL status 00359 */ 00360 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) 00361 { 00362 __IO uint16_t * pSramAddress = (uint16_t *)pAddress; 00363 00364 /* Process Locked */ 00365 __HAL_LOCK(hsram); 00366 00367 /* Update the SRAM controller state */ 00368 hsram->State = HAL_SRAM_STATE_BUSY; 00369 00370 /* Read data from memory */ 00371 for(; BufferSize != 0U; BufferSize--) 00372 { 00373 *pDstBuffer = *(__IO uint16_t *)pSramAddress; 00374 pDstBuffer++; 00375 pSramAddress++; 00376 } 00377 00378 /* Update the SRAM controller state */ 00379 hsram->State = HAL_SRAM_STATE_READY; 00380 00381 /* Process unlocked */ 00382 __HAL_UNLOCK(hsram); 00383 00384 return HAL_OK; 00385 } 00386 00387 /** 00388 * @brief Writes 16-bit buffer to SRAM memory. 00389 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00390 * the configuration information for SRAM module. 00391 * @param pAddress Pointer to write start address 00392 * @param pSrcBuffer Pointer to source buffer to write 00393 * @param BufferSize Size of the buffer to write to memory 00394 * @retval HAL status 00395 */ 00396 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) 00397 { 00398 __IO uint16_t * pSramAddress = (uint16_t *)pAddress; 00399 00400 /* Check the SRAM controller state */ 00401 if(hsram->State == HAL_SRAM_STATE_PROTECTED) 00402 { 00403 return HAL_ERROR; 00404 } 00405 00406 /* Process Locked */ 00407 __HAL_LOCK(hsram); 00408 00409 /* Update the SRAM controller state */ 00410 hsram->State = HAL_SRAM_STATE_BUSY; 00411 00412 /* Write data to memory */ 00413 for(; BufferSize != 0U; BufferSize--) 00414 { 00415 *(__IO uint16_t *)pSramAddress = *pSrcBuffer; 00416 pSrcBuffer++; 00417 pSramAddress++; 00418 } 00419 00420 /* Update the SRAM controller state */ 00421 hsram->State = HAL_SRAM_STATE_READY; 00422 00423 /* Process unlocked */ 00424 __HAL_UNLOCK(hsram); 00425 00426 return HAL_OK; 00427 } 00428 00429 /** 00430 * @brief Reads 32-bit buffer from SRAM memory. 00431 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00432 * the configuration information for SRAM module. 00433 * @param pAddress Pointer to read start address 00434 * @param pDstBuffer Pointer to destination buffer 00435 * @param BufferSize Size of the buffer to read from memory 00436 * @retval HAL status 00437 */ 00438 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) 00439 { 00440 /* Process Locked */ 00441 __HAL_LOCK(hsram); 00442 00443 /* Update the SRAM controller state */ 00444 hsram->State = HAL_SRAM_STATE_BUSY; 00445 00446 /* Read data from memory */ 00447 for(; BufferSize != 0U; BufferSize--) 00448 { 00449 *pDstBuffer = *(__IO uint32_t *)pAddress; 00450 pDstBuffer++; 00451 pAddress++; 00452 } 00453 00454 /* Update the SRAM controller state */ 00455 hsram->State = HAL_SRAM_STATE_READY; 00456 00457 /* Process unlocked */ 00458 __HAL_UNLOCK(hsram); 00459 00460 return HAL_OK; 00461 } 00462 00463 /** 00464 * @brief Writes 32-bit buffer to SRAM memory. 00465 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00466 * the configuration information for SRAM module. 00467 * @param pAddress Pointer to write start address 00468 * @param pSrcBuffer Pointer to source buffer to write 00469 * @param BufferSize Size of the buffer to write to memory 00470 * @retval HAL status 00471 */ 00472 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) 00473 { 00474 /* Check the SRAM controller state */ 00475 if(hsram->State == HAL_SRAM_STATE_PROTECTED) 00476 { 00477 return HAL_ERROR; 00478 } 00479 00480 /* Process Locked */ 00481 __HAL_LOCK(hsram); 00482 00483 /* Update the SRAM controller state */ 00484 hsram->State = HAL_SRAM_STATE_BUSY; 00485 00486 /* Write data to memory */ 00487 for(; BufferSize != 0U; BufferSize--) 00488 { 00489 *(__IO uint32_t *)pAddress = *pSrcBuffer; 00490 pSrcBuffer++; 00491 pAddress++; 00492 } 00493 00494 /* Update the SRAM controller state */ 00495 hsram->State = HAL_SRAM_STATE_READY; 00496 00497 /* Process unlocked */ 00498 __HAL_UNLOCK(hsram); 00499 00500 return HAL_OK; 00501 } 00502 00503 /** 00504 * @brief Reads a Words data from the SRAM memory using DMA transfer. 00505 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00506 * the configuration information for SRAM module. 00507 * @param pAddress Pointer to read start address 00508 * @param pDstBuffer Pointer to destination buffer 00509 * @param BufferSize Size of the buffer to read from memory 00510 * @retval HAL status 00511 */ 00512 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) 00513 { 00514 /* Process Locked */ 00515 __HAL_LOCK(hsram); 00516 00517 /* Update the SRAM controller state */ 00518 hsram->State = HAL_SRAM_STATE_BUSY; 00519 00520 /* Configure DMA user callbacks */ 00521 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; 00522 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; 00523 00524 /* Enable the DMA Stream */ 00525 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); 00526 00527 /* Update the SRAM controller state */ 00528 hsram->State = HAL_SRAM_STATE_READY; 00529 00530 /* Process unlocked */ 00531 __HAL_UNLOCK(hsram); 00532 00533 return HAL_OK; 00534 } 00535 00536 /** 00537 * @brief Writes a Words data buffer to SRAM memory using DMA transfer. 00538 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00539 * the configuration information for SRAM module. 00540 * @param pAddress Pointer to write start address 00541 * @param pSrcBuffer Pointer to source buffer to write 00542 * @param BufferSize Size of the buffer to write to memory 00543 * @retval HAL status 00544 */ 00545 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) 00546 { 00547 /* Check the SRAM controller state */ 00548 if(hsram->State == HAL_SRAM_STATE_PROTECTED) 00549 { 00550 return HAL_ERROR; 00551 } 00552 00553 /* Process Locked */ 00554 __HAL_LOCK(hsram); 00555 00556 /* Update the SRAM controller state */ 00557 hsram->State = HAL_SRAM_STATE_BUSY; 00558 00559 /* Configure DMA user callbacks */ 00560 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; 00561 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; 00562 00563 /* Enable the DMA Stream */ 00564 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); 00565 00566 /* Update the SRAM controller state */ 00567 hsram->State = HAL_SRAM_STATE_READY; 00568 00569 /* Process unlocked */ 00570 __HAL_UNLOCK(hsram); 00571 00572 return HAL_OK; 00573 } 00574 00575 /** 00576 * @} 00577 */ 00578 00579 /** @defgroup SRAM_Exported_Functions_Group3 Control functions 00580 * @brief management functions 00581 * 00582 @verbatim 00583 ============================================================================== 00584 ##### SRAM Control functions ##### 00585 ============================================================================== 00586 [..] 00587 This subsection provides a set of functions allowing to control dynamically 00588 the SRAM interface. 00589 00590 @endverbatim 00591 * @{ 00592 */ 00593 00594 /** 00595 * @brief Enables dynamically SRAM write operation. 00596 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00597 * the configuration information for SRAM module. 00598 * @retval HAL status 00599 */ 00600 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) 00601 { 00602 /* Process Locked */ 00603 __HAL_LOCK(hsram); 00604 00605 /* Enable write operation */ 00606 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); 00607 00608 /* Update the SRAM controller state */ 00609 hsram->State = HAL_SRAM_STATE_READY; 00610 00611 /* Process unlocked */ 00612 __HAL_UNLOCK(hsram); 00613 00614 return HAL_OK; 00615 } 00616 00617 /** 00618 * @brief Disables dynamically SRAM write operation. 00619 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00620 * the configuration information for SRAM module. 00621 * @retval HAL status 00622 */ 00623 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) 00624 { 00625 /* Process Locked */ 00626 __HAL_LOCK(hsram); 00627 00628 /* Update the SRAM controller state */ 00629 hsram->State = HAL_SRAM_STATE_BUSY; 00630 00631 /* Disable write operation */ 00632 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); 00633 00634 /* Update the SRAM controller state */ 00635 hsram->State = HAL_SRAM_STATE_PROTECTED; 00636 00637 /* Process unlocked */ 00638 __HAL_UNLOCK(hsram); 00639 00640 return HAL_OK; 00641 } 00642 00643 /** 00644 * @} 00645 */ 00646 00647 /** @defgroup SRAM_Exported_Functions_Group4 State functions 00648 * @brief Peripheral State functions 00649 * 00650 @verbatim 00651 ============================================================================== 00652 ##### SRAM State functions ##### 00653 ============================================================================== 00654 [..] 00655 This subsection permits to get in run-time the status of the SRAM controller 00656 and the data flow. 00657 00658 @endverbatim 00659 * @{ 00660 */ 00661 00662 /** 00663 * @brief Returns the SRAM controller state 00664 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00665 * the configuration information for SRAM module. 00666 * @retval HAL state 00667 */ 00668 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) 00669 { 00670 return hsram->State; 00671 } 00672 /** 00673 * @} 00674 */ 00675 00676 /** 00677 * @} 00678 */ 00679 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ 00680 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ 00681 STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00682 #endif /* HAL_SRAM_MODULE_ENABLED */ 00683 /** 00684 * @} 00685 */ 00686 00687 /** 00688 * @} 00689 */ 00690 00691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/