STM32F439xx HAL User Manual
stm32f4xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @brief   RCC HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + Peripheral Control functions
00010   *
00011   @verbatim
00012   ==============================================================================
00013                       ##### RCC specific features #####
00014   ==============================================================================
00015     [..]
00016       After reset the device is running from Internal High Speed oscillator
00017       (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
00018       and I-Cache are disabled, and all peripherals are off except internal
00019       SRAM, Flash and JTAG.
00020       (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
00021           all peripherals mapped on these busses are running at HSI speed.
00022       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00023       (+) All GPIOs are in input floating state, except the JTAG pins which
00024           are assigned to be used for debug purpose.
00025 
00026     [..]
00027       Once the device started from reset, the user application has to:
00028       (+) Configure the clock source to be used to drive the System clock
00029           (if the application needs higher frequency/performance)
00030       (+) Configure the System clock frequency and Flash settings
00031       (+) Configure the AHB and APB busses prescalers
00032       (+) Enable the clock for the peripheral(s) to be used
00033       (+) Configure the clock source(s) for peripherals which clocks are not
00034           derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
00035 
00036                       ##### RCC Limitations #####
00037   ==============================================================================
00038     [..]
00039       A delay between an RCC peripheral clock enable and the effective peripheral
00040       enabling should be taken into account in order to manage the peripheral read/write
00041       from/to registers.
00042       (+) This delay depends on the peripheral mapping.
00043       (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
00044           after the clock enable bit is set on the hardware register
00045       (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
00046           after the clock enable bit is set on the hardware register
00047 
00048     [..]
00049       Implemented Workaround:
00050       (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
00051           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
00052 
00053   @endverbatim
00054   ******************************************************************************
00055   * @attention
00056   *
00057   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00058   *
00059   * Redistribution and use in source and binary forms, with or without modification,
00060   * are permitted provided that the following conditions are met:
00061   *   1. Redistributions of source code must retain the above copyright notice,
00062   *      this list of conditions and the following disclaimer.
00063   *   2. Redistributions in binary form must reproduce the above copyright notice,
00064   *      this list of conditions and the following disclaimer in the documentation
00065   *      and/or other materials provided with the distribution.
00066   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00067   *      may be used to endorse or promote products derived from this software
00068   *      without specific prior written permission.
00069   *
00070   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00071   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00072   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00073   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00074   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00075   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00076   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00077   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00078   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00079   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00080   *
00081   ******************************************************************************
00082   */
00083 
00084 /* Includes ------------------------------------------------------------------*/
00085 #include "stm32f4xx_hal.h"
00086 
00087 /** @addtogroup STM32F4xx_HAL_Driver
00088   * @{
00089   */
00090 
00091 /** @defgroup RCC RCC
00092   * @brief RCC HAL module driver
00093   * @{
00094   */
00095 
00096 #ifdef HAL_RCC_MODULE_ENABLED
00097 
00098 /* Private typedef -----------------------------------------------------------*/
00099 /* Private define ------------------------------------------------------------*/
00100 /** @addtogroup RCC_Private_Constants
00101   * @{
00102   */
00103 
00104 /* Private macro -------------------------------------------------------------*/
00105 #define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
00106 #define MCO1_GPIO_PORT        GPIOA
00107 #define MCO1_PIN              GPIO_PIN_8
00108 
00109 #define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
00110 #define MCO2_GPIO_PORT         GPIOC
00111 #define MCO2_PIN               GPIO_PIN_9
00112 /**
00113   * @}
00114   */
00115 
00116 /* Private variables ---------------------------------------------------------*/
00117 /** @defgroup RCC_Private_Variables RCC Private Variables
00118   * @{
00119   */
00120 /**
00121   * @}
00122   */
00123 /* Private function prototypes -----------------------------------------------*/
00124 /* Private functions ---------------------------------------------------------*/
00125 
00126 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00127   *  @{
00128   */
00129 
00130 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00131  *  @brief    Initialization and Configuration functions
00132  *
00133 @verbatim
00134  ===============================================================================
00135            ##### Initialization and de-initialization functions #####
00136  ===============================================================================
00137     [..]
00138       This section provides functions allowing to configure the internal/external oscillators
00139       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
00140        and APB2).
00141 
00142     [..] Internal/external clock and PLL configuration
00143          (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
00144              the PLL as System clock source.
00145 
00146          (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
00147              clock source.
00148 
00149          (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
00150              through the PLL as System clock source. Can be used also as RTC clock source.
00151 
00152          (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
00153 
00154          (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
00155            (++) The first output is used to generate the high speed system clock (up to 168 MHz)
00156            (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
00157                 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
00158 
00159          (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
00160              and if a HSE clock failure occurs(HSE used directly or through PLL as System
00161              clock source), the System clocks automatically switched to HSI and an interrupt
00162              is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
00163              (Non-Maskable Interrupt) exception vector.
00164 
00165          (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
00166              clock (through a configurable prescaler) on PA8 pin.
00167 
00168          (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
00169              clock (through a configurable prescaler) on PC9 pin.
00170 
00171     [..] System, AHB and APB busses clocks configuration
00172          (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
00173              HSE and PLL.
00174              The AHB clock (HCLK) is derived from System clock through configurable
00175              prescaler and used to clock the CPU, memory and peripherals mapped
00176              on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
00177              from AHB clock through configurable prescalers and used to clock
00178              the peripherals mapped on these busses. You can use
00179              "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00180 
00181          (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
00182              frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
00183              Depending on the device voltage range, the maximum frequency should
00184              be adapted accordingly (refer to the product datasheets for more details).
00185 
00186          (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
00187              the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
00188              Depending on the device voltage range, the maximum frequency should
00189              be adapted accordingly (refer to the product datasheets for more details).
00190 
00191          (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
00192              PCLK2 84 MHz and PCLK1 42 MHz.
00193              Depending on the device voltage range, the maximum frequency should
00194              be adapted accordingly (refer to the product datasheets for more details).
00195 
00196          (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
00197              PCLK2 100 MHz and PCLK1 50 MHz.
00198              Depending on the device voltage range, the maximum frequency should
00199              be adapted accordingly (refer to the product datasheets for more details).
00200 
00201 @endverbatim
00202   * @{
00203   */
00204 
00205 /**
00206   * @brief  Resets the RCC clock configuration to the default reset state.
00207   * @note   The default reset state of the clock configuration is given below:
00208   *            - HSI ON and used as system clock source
00209   *            - HSE and PLL OFF
00210   *            - AHB, APB1 and APB2 prescaler set to 1.
00211   *            - CSS, MCO1 and MCO2 OFF
00212   *            - All interrupts disabled
00213   * @note   This function doesn't modify the configuration of the
00214   *            - Peripheral clocks
00215   *            - LSI, LSE and RTC clocks
00216   * @retval HAL status
00217   */
00218 __weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
00219 {
00220   return HAL_OK;
00221 }
00222 
00223 /**
00224   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
00225   *         RCC_OscInitTypeDef.
00226   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
00227   *         contains the configuration information for the RCC Oscillators.
00228   * @note   The PLL is not disabled when used as system clock.
00229   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
00230   *         supported by this API. User should request a transition to LSE Off
00231   *         first and then LSE On or LSE Bypass.
00232   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00233   *         supported by this API. User should request a transition to HSE Off
00234   *         first and then HSE On or HSE Bypass.
00235   * @retval HAL status
00236   */
00237 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00238 {
00239   uint32_t tickstart;
00240 
00241   /* Check Null pointer */
00242   if(RCC_OscInitStruct == NULL)
00243   {
00244     return HAL_ERROR;
00245   }
00246 
00247   /* Check the parameters */
00248   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00249   /*------------------------------- HSE Configuration ------------------------*/
00250   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00251   {
00252     /* Check the parameters */
00253     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00254     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
00255     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
00256       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
00257     {
00258       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00259       {
00260         return HAL_ERROR;
00261       }
00262     }
00263     else
00264     {
00265       /* Set the new HSE configuration ---------------------------------------*/
00266       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00267 
00268       /* Check the HSE State */
00269       if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
00270       {
00271         /* Get Start Tick */
00272         tickstart = HAL_GetTick();
00273 
00274         /* Wait till HSE is ready */
00275         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00276         {
00277           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00278           {
00279             return HAL_TIMEOUT;
00280           }
00281         }
00282       }
00283       else
00284       {
00285         /* Get Start Tick */
00286         tickstart = HAL_GetTick();
00287 
00288         /* Wait till HSE is bypassed or disabled */
00289         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
00290         {
00291           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00292           {
00293             return HAL_TIMEOUT;
00294           }
00295         }
00296       }
00297     }
00298   }
00299   /*----------------------------- HSI Configuration --------------------------*/
00300   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00301   {
00302     /* Check the parameters */
00303     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00304     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00305 
00306     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
00307     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
00308       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
00309     {
00310       /* When HSI is used as system clock it will not disabled */
00311       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
00312       {
00313         return HAL_ERROR;
00314       }
00315       /* Otherwise, just the calibration is allowed */
00316       else
00317       {
00318         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00319         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00320       }
00321     }
00322     else
00323     {
00324       /* Check the HSI State */
00325       if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
00326       {
00327         /* Enable the Internal High Speed oscillator (HSI). */
00328         __HAL_RCC_HSI_ENABLE();
00329 
00330         /* Get Start Tick*/
00331         tickstart = HAL_GetTick();
00332 
00333         /* Wait till HSI is ready */
00334         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00335         {
00336           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00337           {
00338             return HAL_TIMEOUT;
00339           }
00340         }
00341 
00342         /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
00343         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00344       }
00345       else
00346       {
00347         /* Disable the Internal High Speed oscillator (HSI). */
00348         __HAL_RCC_HSI_DISABLE();
00349 
00350         /* Get Start Tick*/
00351         tickstart = HAL_GetTick();
00352 
00353         /* Wait till HSI is ready */
00354         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
00355         {
00356           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00357           {
00358             return HAL_TIMEOUT;
00359           }
00360         }
00361       }
00362     }
00363   }
00364   /*------------------------------ LSI Configuration -------------------------*/
00365   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00366   {
00367     /* Check the parameters */
00368     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00369 
00370     /* Check the LSI State */
00371     if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
00372     {
00373       /* Enable the Internal Low Speed oscillator (LSI). */
00374       __HAL_RCC_LSI_ENABLE();
00375 
00376       /* Get Start Tick*/
00377       tickstart = HAL_GetTick();
00378 
00379       /* Wait till LSI is ready */
00380       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
00381       {
00382         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00383         {
00384           return HAL_TIMEOUT;
00385         }
00386       }
00387     }
00388     else
00389     {
00390       /* Disable the Internal Low Speed oscillator (LSI). */
00391       __HAL_RCC_LSI_DISABLE();
00392 
00393       /* Get Start Tick */
00394       tickstart = HAL_GetTick();
00395 
00396       /* Wait till LSI is ready */
00397       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
00398       {
00399         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00400         {
00401           return HAL_TIMEOUT;
00402         }
00403       }
00404     }
00405   }
00406   /*------------------------------ LSE Configuration -------------------------*/
00407   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00408   {
00409     FlagStatus       pwrclkchanged = RESET;
00410 
00411     /* Check the parameters */
00412     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00413 
00414     /* Update LSE configuration in Backup Domain control register    */
00415     /* Requires to enable write access to Backup Domain of necessary */
00416     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
00417     {
00418       __HAL_RCC_PWR_CLK_ENABLE();
00419       pwrclkchanged = SET;
00420     }
00421 
00422     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00423     {
00424       /* Enable write access to Backup domain */
00425       SET_BIT(PWR->CR, PWR_CR_DBP);
00426 
00427       /* Wait for Backup domain Write protection disable */
00428       tickstart = HAL_GetTick();
00429 
00430       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00431       {
00432         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00433         {
00434           return HAL_TIMEOUT;
00435         }
00436       }
00437     }
00438 
00439     /* Set the new LSE configuration -----------------------------------------*/
00440     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00441     /* Check the LSE State */
00442     if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
00443     {
00444       /* Get Start Tick*/
00445       tickstart = HAL_GetTick();
00446 
00447       /* Wait till LSE is ready */
00448       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00449       {
00450         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00451         {
00452           return HAL_TIMEOUT;
00453         }
00454       }
00455     }
00456     else
00457     {
00458       /* Get Start Tick */
00459       tickstart = HAL_GetTick();
00460 
00461       /* Wait till LSE is ready */
00462       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
00463       {
00464         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00465         {
00466           return HAL_TIMEOUT;
00467         }
00468       }
00469     }
00470 
00471     /* Restore clock configuration if changed */
00472     if(pwrclkchanged == SET)
00473     {
00474       __HAL_RCC_PWR_CLK_DISABLE();
00475     }
00476   }
00477   /*-------------------------------- PLL Configuration -----------------------*/
00478   /* Check the parameters */
00479   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00480   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
00481   {
00482     /* Check if the PLL is used as system clock or not */
00483     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
00484     {
00485       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
00486       {
00487         /* Check the parameters */
00488         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00489         assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
00490         assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
00491         assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
00492         assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
00493 
00494         /* Disable the main PLL. */
00495         __HAL_RCC_PLL_DISABLE();
00496 
00497         /* Get Start Tick */
00498         tickstart = HAL_GetTick();
00499 
00500         /* Wait till PLL is ready */
00501         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00502         {
00503           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00504           {
00505             return HAL_TIMEOUT;
00506           }
00507         }
00508 
00509         /* Configure the main PLL clock source, multiplication and division factors. */
00510         WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
00511                                  RCC_OscInitStruct->PLL.PLLM                                                 | \
00512                                  (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
00513                                  (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
00514                                  (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
00515         /* Enable the main PLL. */
00516         __HAL_RCC_PLL_ENABLE();
00517 
00518         /* Get Start Tick */
00519         tickstart = HAL_GetTick();
00520 
00521         /* Wait till PLL is ready */
00522         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00523         {
00524           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00525           {
00526             return HAL_TIMEOUT;
00527           }
00528         }
00529       }
00530       else
00531       {
00532         /* Disable the main PLL. */
00533         __HAL_RCC_PLL_DISABLE();
00534 
00535         /* Get Start Tick */
00536         tickstart = HAL_GetTick();
00537 
00538         /* Wait till PLL is ready */
00539         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
00540         {
00541           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00542           {
00543             return HAL_TIMEOUT;
00544           }
00545         }
00546       }
00547     }
00548     else
00549     {
00550       return HAL_ERROR;
00551     }
00552   }
00553   return HAL_OK;
00554 }
00555 
00556 /**
00557   * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
00558   *         parameters in the RCC_ClkInitStruct.
00559   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
00560   *         contains the configuration information for the RCC peripheral.
00561   * @param  FLatency FLASH Latency, this parameter depend on device selected
00562   *
00563   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00564   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
00565   *
00566   * @note   The HSI is used (enabled by hardware) as system clock source after
00567   *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
00568   *         of failure of the HSE used directly or indirectly as system clock
00569   *         (if the Clock Security System CSS is enabled).
00570   *
00571   * @note   A switch from one clock source to another occurs only if the target
00572   *         clock source is ready (clock stable after startup delay or PLL locked).
00573   *         If a clock source which is not yet ready is selected, the switch will
00574   *         occur when the clock source will be ready.
00575   *
00576   * @note   Depending on the device voltage range, the software has to set correctly
00577   *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
00578   *         (for more details refer to section above "Initialization/de-initialization functions")
00579   * @retval None
00580   */
00581 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00582 {
00583   uint32_t tickstart;
00584 
00585   /* Check Null pointer */
00586   if(RCC_ClkInitStruct == NULL)
00587   {
00588     return HAL_ERROR;
00589   }
00590 
00591   /* Check the parameters */
00592   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00593   assert_param(IS_FLASH_LATENCY(FLatency));
00594 
00595   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00596     must be correctly programmed according to the frequency of the CPU clock
00597     (HCLK) and the supply voltage of the device. */
00598 
00599   /* Increasing the number of wait states because of higher CPU frequency */
00600   if(FLatency > __HAL_FLASH_GET_LATENCY())
00601   {
00602     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00603     __HAL_FLASH_SET_LATENCY(FLatency);
00604 
00605     /* Check that the new number of wait states is taken into account to access the Flash
00606     memory by reading the FLASH_ACR register */
00607     if(__HAL_FLASH_GET_LATENCY() != FLatency)
00608     {
00609       return HAL_ERROR;
00610     }
00611   }
00612 
00613   /*-------------------------- HCLK Configuration --------------------------*/
00614   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00615   {
00616     /* Set the highest APBx dividers in order to ensure that we do not go through
00617        a non-spec phase whatever we decrease or increase HCLK. */
00618     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00619     {
00620       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
00621     }
00622 
00623     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00624     {
00625       MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
00626     }
00627 
00628     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00629     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00630   }
00631 
00632   /*------------------------- SYSCLK Configuration ---------------------------*/
00633   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00634   {
00635     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00636 
00637     /* HSE is selected as System Clock Source */
00638     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00639     {
00640       /* Check the HSE ready flag */
00641       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00642       {
00643         return HAL_ERROR;
00644       }
00645     }
00646     /* PLL is selected as System Clock Source */
00647     else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
00648             (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
00649     {
00650       /* Check the PLL ready flag */
00651       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00652       {
00653         return HAL_ERROR;
00654       }
00655     }
00656     /* HSI is selected as System Clock Source */
00657     else
00658     {
00659       /* Check the HSI ready flag */
00660       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00661       {
00662         return HAL_ERROR;
00663       }
00664     }
00665 
00666     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
00667 
00668     /* Get Start Tick */
00669     tickstart = HAL_GetTick();
00670 
00671     while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
00672     {
00673       if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
00674       {
00675         return HAL_TIMEOUT;
00676       }
00677     }
00678   }
00679 
00680   /* Decreasing the number of wait states because of lower CPU frequency */
00681   if(FLatency < __HAL_FLASH_GET_LATENCY())
00682   {
00683      /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00684     __HAL_FLASH_SET_LATENCY(FLatency);
00685 
00686     /* Check that the new number of wait states is taken into account to access the Flash
00687     memory by reading the FLASH_ACR register */
00688     if(__HAL_FLASH_GET_LATENCY() != FLatency)
00689     {
00690       return HAL_ERROR;
00691     }
00692   }
00693 
00694   /*-------------------------- PCLK1 Configuration ---------------------------*/
00695   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00696   {
00697     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
00698     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
00699   }
00700 
00701   /*-------------------------- PCLK2 Configuration ---------------------------*/
00702   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00703   {
00704     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
00705     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
00706   }
00707 
00708   /* Update the SystemCoreClock global variable */
00709   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
00710 
00711   /* Configure the source of time base considering new system clocks settings */
00712   HAL_InitTick (TICK_INT_PRIORITY);
00713 
00714   return HAL_OK;
00715 }
00716 
00717 /**
00718   * @}
00719   */
00720 
00721 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
00722  *  @brief   RCC clocks control functions
00723  *
00724 @verbatim
00725  ===============================================================================
00726                       ##### Peripheral Control functions #####
00727  ===============================================================================
00728     [..]
00729     This subsection provides a set of functions allowing to control the RCC Clocks
00730     frequencies.
00731 
00732 @endverbatim
00733   * @{
00734   */
00735 
00736 /**
00737   * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
00738   * @note   PA8/PC9 should be configured in alternate function mode.
00739   * @param  RCC_MCOx specifies the output direction for the clock source.
00740   *          This parameter can be one of the following values:
00741   *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
00742   *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
00743   * @param  RCC_MCOSource specifies the clock source to output.
00744   *          This parameter can be one of the following values:
00745   *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
00746   *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
00747   *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
00748   *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
00749   *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
00750   *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
00751   *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
00752   *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
00753   *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
00754   * @param  RCC_MCODiv specifies the MCOx prescaler.
00755   *          This parameter can be one of the following values:
00756   *            @arg RCC_MCODIV_1: no division applied to MCOx clock
00757   *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
00758   *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
00759   *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
00760   *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
00761   * @note  For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
00762   *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
00763   * @retval None
00764   */
00765 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
00766 {
00767   GPIO_InitTypeDef GPIO_InitStruct;
00768   /* Check the parameters */
00769   assert_param(IS_RCC_MCO(RCC_MCOx));
00770   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
00771   /* RCC_MCO1 */
00772   if(RCC_MCOx == RCC_MCO1)
00773   {
00774     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
00775 
00776     /* MCO1 Clock Enable */
00777     __MCO1_CLK_ENABLE();
00778 
00779     /* Configure the MCO1 pin in alternate function mode */
00780     GPIO_InitStruct.Pin = MCO1_PIN;
00781     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00782     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
00783     GPIO_InitStruct.Pull = GPIO_NOPULL;
00784     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
00785     HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
00786 
00787     /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
00788     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
00789 
00790    /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
00791 #if defined(RCC_CFGR_MCO1EN)
00792     __HAL_RCC_MCO1_ENABLE();
00793 #endif /* RCC_CFGR_MCO1EN */
00794   }
00795 #if defined(RCC_CFGR_MCO2)
00796   else
00797   {
00798     assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
00799 
00800     /* MCO2 Clock Enable */
00801     __MCO2_CLK_ENABLE();
00802 
00803     /* Configure the MCO2 pin in alternate function mode */
00804     GPIO_InitStruct.Pin = MCO2_PIN;
00805     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
00806     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
00807     GPIO_InitStruct.Pull = GPIO_NOPULL;
00808     GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
00809     HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
00810 
00811     /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
00812     MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
00813 
00814    /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
00815 #if defined(RCC_CFGR_MCO2EN)
00816     __HAL_RCC_MCO2_ENABLE();
00817 #endif /* RCC_CFGR_MCO2EN */
00818   }
00819 #endif /* RCC_CFGR_MCO2 */
00820 }
00821 
00822 /**
00823   * @brief  Enables the Clock Security System.
00824   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
00825   *         is automatically disabled and an interrupt is generated to inform the
00826   *         software about the failure (Clock Security System Interrupt, CSSI),
00827   *         allowing the MCU to perform rescue operations. The CSSI is linked to
00828   *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
00829   * @retval None
00830   */
00831 void HAL_RCC_EnableCSS(void)
00832 {
00833   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
00834 }
00835 
00836 /**
00837   * @brief  Disables the Clock Security System.
00838   * @retval None
00839   */
00840 void HAL_RCC_DisableCSS(void)
00841 {
00842   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
00843 }
00844 
00845 /**
00846   * @brief  Returns the SYSCLK frequency
00847   *
00848   * @note   The system frequency computed by this function is not the real
00849   *         frequency in the chip. It is calculated based on the predefined
00850   *         constant and the selected clock source:
00851   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
00852   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
00853   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
00854   *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
00855   * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
00856   *               16 MHz) but the real value may vary depending on the variations
00857   *               in voltage and temperature.
00858   * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
00859   *                25 MHz), user has to ensure that HSE_VALUE is same as the real
00860   *                frequency of the crystal used. Otherwise, this function may
00861   *                have wrong result.
00862   *
00863   * @note   The result of this function could be not correct when using fractional
00864   *         value for HSE crystal.
00865   *
00866   * @note   This function can be used by the user application to compute the
00867   *         baudrate for the communication peripherals or configure other parameters.
00868   *
00869   * @note   Each time SYSCLK changes, this function must be called to update the
00870   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
00871   *
00872   *
00873   * @retval SYSCLK frequency
00874   */
00875 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
00876 {
00877   uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
00878   uint32_t sysclockfreq = 0U;
00879 
00880   /* Get SYSCLK source -------------------------------------------------------*/
00881   switch (RCC->CFGR & RCC_CFGR_SWS)
00882   {
00883     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
00884     {
00885       sysclockfreq = HSI_VALUE;
00886        break;
00887     }
00888     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
00889     {
00890       sysclockfreq = HSE_VALUE;
00891       break;
00892     }
00893     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
00894     {
00895       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
00896       SYSCLK = PLL_VCO / PLLP */
00897       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
00898       if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
00899       {
00900         /* HSE used as PLL clock source */
00901         pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
00902       }
00903       else
00904       {
00905         /* HSI used as PLL clock source */
00906         pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
00907       }
00908       pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
00909 
00910       sysclockfreq = pllvco/pllp;
00911       break;
00912     }
00913     default:
00914     {
00915       sysclockfreq = HSI_VALUE;
00916       break;
00917     }
00918   }
00919   return sysclockfreq;
00920 }
00921 
00922 /**
00923   * @brief  Returns the HCLK frequency
00924   * @note   Each time HCLK changes, this function must be called to update the
00925   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
00926   *
00927   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00928   *         and updated within this function
00929   * @retval HCLK frequency
00930   */
00931 uint32_t HAL_RCC_GetHCLKFreq(void)
00932 {
00933   return SystemCoreClock;
00934 }
00935 
00936 /**
00937   * @brief  Returns the PCLK1 frequency
00938   * @note   Each time PCLK1 changes, this function must be called to update the
00939   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
00940   * @retval PCLK1 frequency
00941   */
00942 uint32_t HAL_RCC_GetPCLK1Freq(void)
00943 {
00944   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
00945   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
00946 }
00947 
00948 /**
00949   * @brief  Returns the PCLK2 frequency
00950   * @note   Each time PCLK2 changes, this function must be called to update the
00951   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
00952   * @retval PCLK2 frequency
00953   */
00954 uint32_t HAL_RCC_GetPCLK2Freq(void)
00955 {
00956   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
00957   return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
00958 }
00959 
00960 /**
00961   * @brief  Configures the RCC_OscInitStruct according to the internal
00962   * RCC configuration registers.
00963   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
00964   * will be configured.
00965   * @retval None
00966   */
00967 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00968 {
00969   /* Set all possible values for the Oscillator type parameter ---------------*/
00970   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
00971 
00972   /* Get the HSE configuration -----------------------------------------------*/
00973   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
00974   {
00975     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
00976   }
00977   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
00978   {
00979     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
00980   }
00981   else
00982   {
00983     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
00984   }
00985 
00986   /* Get the HSI configuration -----------------------------------------------*/
00987   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
00988   {
00989     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
00990   }
00991   else
00992   {
00993     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
00994   }
00995 
00996   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
00997 
00998   /* Get the LSE configuration -----------------------------------------------*/
00999   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01000   {
01001     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01002   }
01003   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01004   {
01005     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01006   }
01007   else
01008   {
01009     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01010   }
01011 
01012   /* Get the LSI configuration -----------------------------------------------*/
01013   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
01014   {
01015     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01016   }
01017   else
01018   {
01019     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01020   }
01021 
01022   /* Get the PLL configuration -----------------------------------------------*/
01023   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
01024   {
01025     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01026   }
01027   else
01028   {
01029     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01030   }
01031   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
01032   RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
01033   RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
01034   RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
01035   RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
01036 }
01037 
01038 /**
01039   * @brief  Configures the RCC_ClkInitStruct according to the internal
01040   * RCC configuration registers.
01041   * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
01042   * will be configured.
01043   * @param  pFLatency Pointer on the Flash Latency.
01044   * @retval None
01045   */
01046 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01047 {
01048   /* Set all possible values for the Clock type parameter --------------------*/
01049   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
01050 
01051   /* Get the SYSCLK configuration --------------------------------------------*/
01052   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01053 
01054   /* Get the HCLK configuration ----------------------------------------------*/
01055   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
01056 
01057   /* Get the APB1 configuration ----------------------------------------------*/
01058   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
01059 
01060   /* Get the APB2 configuration ----------------------------------------------*/
01061   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
01062 
01063   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01064   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01065 }
01066 
01067 /**
01068   * @brief This function handles the RCC CSS interrupt request.
01069   * @note This API should be called under the NMI_Handler().
01070   * @retval None
01071   */
01072 void HAL_RCC_NMI_IRQHandler(void)
01073 {
01074   /* Check RCC CSSF flag  */
01075   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01076   {
01077     /* RCC Clock Security System interrupt user callback */
01078     HAL_RCC_CSSCallback();
01079 
01080     /* Clear RCC CSS pending bit */
01081     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01082   }
01083 }
01084 
01085 /**
01086   * @brief  RCC Clock Security System interrupt callback
01087   * @retval None
01088   */
01089 __weak void HAL_RCC_CSSCallback(void)
01090 {
01091   /* NOTE : This function Should not be modified, when the callback is needed,
01092             the HAL_RCC_CSSCallback could be implemented in the user file
01093    */
01094 }
01095 
01096 /**
01097   * @}
01098   */
01099 
01100 /**
01101   * @}
01102   */
01103 
01104 #endif /* HAL_RCC_MODULE_ENABLED */
01105 /**
01106   * @}
01107   */
01108 
01109 /**
01110   * @}
01111   */
01112 
01113 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/