STM32F439xx HAL User Manual: stm32f4xx_hal

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f4xx_hal.h"

Go to the source code of this file.

Defines
#define	__MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define	MCO1_GPIO_PORT GPIOA
#define	MCO1_PIN GPIO_PIN_8
#define	__MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define	MCO2_GPIO_PORT GPIOC
#define	MCO2_PIN GPIO_PIN_9
Functions
__weak HAL_StatusTypeDef	HAL_RCC_DeInit (void)
	Resets the RCC clock configuration to the default reset state.
__weak HAL_StatusTypeDef	HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
	Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef	HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
	Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.
void	HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
	Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
void	HAL_RCC_EnableCSS (void)
	Enables the Clock Security System.
void	HAL_RCC_DisableCSS (void)
	Disables the Clock Security System.
__weak uint32_t	HAL_RCC_GetSysClockFreq (void)
	Returns the SYSCLK frequency.
uint32_t	HAL_RCC_GetHCLKFreq (void)
	Returns the HCLK frequency.
uint32_t	HAL_RCC_GetPCLK1Freq (void)
	Returns the PCLK1 frequency.
uint32_t	HAL_RCC_GetPCLK2Freq (void)
	Returns the PCLK2 frequency.
__weak void	HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
	Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void	HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)
	Configures the RCC_ClkInitStruct according to the internal RCC configuration registers.
void	HAL_RCC_NMI_IRQHandler (void)
	This function handles the RCC CSS interrupt request.
__weak void	HAL_RCC_CSSCallback (void)
	RCC Clock Security System interrupt callback.

Detailed Description

Author:

MCD Application Team

  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Internal High Speed oscillator
      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
      and I-Cache are disabled, and all peripherals are off except internal
      SRAM, Flash and JTAG.
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
          all peripherals mapped on these busses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in input floating state, except the JTAG pins which
          are assigned to be used for debug purpose.

    [..]
      Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB busses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals which clocks are not
          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
          after the clock enable bit is set on the hardware register
      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
          after the clock enable bit is set on the hardware register

    [..]
      Implemented Workaround:
      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.

Attention:

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Definition in file stm32f4xx_hal_rcc.c.

Defines

Functions

Detailed Description

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