|
STM32F439xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_qspi.h 00004 * @author MCD Application Team 00005 * @brief Header file of QSPI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_HAL_QSPI_H 00038 #define __STM32F4xx_HAL_QSPI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ 00045 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32f4xx_hal_def.h" 00048 00049 /** @addtogroup STM32F4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup QSPI 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup QSPI_Exported_Types QSPI Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief QSPI Init structure definition 00064 */ 00065 00066 typedef struct 00067 { 00068 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 00069 This parameter can be a number between 0 and 255 */ 00070 00071 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 00072 This parameter can be a value between 1 and 32 */ 00073 00074 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 00075 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 00076 This parameter can be a value of @ref QSPI_SampleShifting */ 00077 00078 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 00079 required to address the flash memory. The flash capacity can be up to 4GB 00080 (addressed using 32 bits) in indirect mode, but the addressable space in 00081 memory-mapped mode is limited to 256MB 00082 This parameter can be a number between 0 and 31 */ 00083 00084 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 00085 of clock cycles which the chip select must remain high between commands. 00086 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 00087 00088 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 00089 This parameter can be a value of @ref QSPI_ClockMode */ 00090 00091 uint32_t FlashID; /* Specifies the Flash which will be used, 00092 This parameter can be a value of @ref QSPI_Flash_Select */ 00093 00094 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 00095 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 00096 }QSPI_InitTypeDef; 00097 00098 /** 00099 * @brief HAL QSPI State structures definition 00100 */ 00101 typedef enum 00102 { 00103 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 00104 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 00105 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 00106 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 00107 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 00108 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 00109 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 00110 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 00111 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 00112 }HAL_QSPI_StateTypeDef; 00113 00114 /** 00115 * @brief QSPI Handle Structure definition 00116 */ 00117 typedef struct 00118 { 00119 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 00120 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 00121 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 00122 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 00123 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 00124 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 00125 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 00126 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 00127 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 00128 __IO HAL_LockTypeDef Lock; /* Locking object */ 00129 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 00130 __IO uint32_t ErrorCode; /* QSPI Error code */ 00131 uint32_t Timeout; /* Timeout for the QSPI memory access */ 00132 }QSPI_HandleTypeDef; 00133 00134 /** 00135 * @brief QSPI Command structure definition 00136 */ 00137 typedef struct 00138 { 00139 uint32_t Instruction; /* Specifies the Instruction to be sent 00140 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 00141 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 00142 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ 00143 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 00144 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ 00145 uint32_t AddressSize; /* Specifies the Address Size 00146 This parameter can be a value of @ref QSPI_AddressSize */ 00147 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 00148 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 00149 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 00150 This parameter can be a number between 0 and 31 */ 00151 uint32_t InstructionMode; /* Specifies the Instruction Mode 00152 This parameter can be a value of @ref QSPI_InstructionMode */ 00153 uint32_t AddressMode; /* Specifies the Address Mode 00154 This parameter can be a value of @ref QSPI_AddressMode */ 00155 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 00156 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 00157 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 00158 This parameter can be a value of @ref QSPI_DataMode */ 00159 uint32_t NbData; /* Specifies the number of data to transfer. 00160 This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length 00161 until end of memory)*/ 00162 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 00163 This parameter can be a value of @ref QSPI_DdrMode */ 00164 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of 00165 system clock in DDR mode. 00166 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 00167 uint32_t SIOOMode; /* Specifies the send instruction only once mode 00168 This parameter can be a value of @ref QSPI_SIOOMode */ 00169 }QSPI_CommandTypeDef; 00170 00171 /** 00172 * @brief QSPI Auto Polling mode configuration structure definition 00173 */ 00174 typedef struct 00175 { 00176 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 00177 This parameter can be any value between 0 and 0xFFFFFFFFU */ 00178 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 00179 This parameter can be any value between 0 and 0xFFFFFFFFU */ 00180 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 00181 This parameter can be any value between 0 and 0xFFFFU */ 00182 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 00183 This parameter can be any value between 1 and 4 */ 00184 uint32_t MatchMode; /* Specifies the method used for determining a match. 00185 This parameter can be a value of @ref QSPI_MatchMode */ 00186 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 00187 This parameter can be a value of @ref QSPI_AutomaticStop */ 00188 }QSPI_AutoPollingTypeDef; 00189 00190 /** 00191 * @brief QSPI Memory Mapped mode configuration structure definition 00192 */ 00193 typedef struct 00194 { 00195 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 00196 This parameter can be any value between 0 and 0xFFFFU */ 00197 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. 00198 This parameter can be a value of @ref QSPI_TimeOutActivation */ 00199 }QSPI_MemoryMappedTypeDef; 00200 /** 00201 * @} 00202 */ 00203 00204 /* Exported constants --------------------------------------------------------*/ 00205 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 00206 * @{ 00207 */ 00208 /** @defgroup QSPI_ErrorCode QSPI Error Code 00209 * @{ 00210 */ 00211 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 00212 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 00213 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 00214 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 00215 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 00216 /** 00217 * @} 00218 */ 00219 00220 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 00221 * @{ 00222 */ 00223 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 00224 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 00225 /** 00226 * @} 00227 */ 00228 00229 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time 00230 * @{ 00231 */ 00232 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 00233 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 00234 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 00235 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 00236 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 00237 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 00238 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 00239 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup QSPI_ClockMode QSPI Clock Mode 00245 * @{ 00246 */ 00247 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 00248 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 00249 /** 00250 * @} 00251 */ 00252 00253 /** @defgroup QSPI_Flash_Select QSPI Flash Select 00254 * @{ 00255 */ 00256 #define QSPI_FLASH_ID_1 0x00000000U 00257 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) 00258 /** 00259 * @} 00260 */ 00261 00262 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 00263 * @{ 00264 */ 00265 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) 00266 #define QSPI_DUALFLASH_DISABLE 0x00000000U 00267 /** 00268 * @} 00269 */ 00270 00271 /** @defgroup QSPI_AddressSize QSPI Address Size 00272 * @{ 00273 */ 00274 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 00275 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 00276 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 00277 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 00278 /** 00279 * @} 00280 */ 00281 00282 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 00283 * @{ 00284 */ 00285 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 00286 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 00287 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 00288 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 00289 /** 00290 * @} 00291 */ 00292 00293 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 00294 * @{ 00295 */ 00296 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 00297 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 00298 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 00299 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 00300 /** 00301 * @} 00302 */ 00303 00304 /** @defgroup QSPI_AddressMode QSPI Address Mode 00305 * @{ 00306 */ 00307 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 00308 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 00309 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 00310 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 00311 /** 00312 * @} 00313 */ 00314 00315 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 00316 * @{ 00317 */ 00318 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 00319 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 00320 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 00321 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 00322 /** 00323 * @} 00324 */ 00325 00326 /** @defgroup QSPI_DataMode QSPI Data Mode 00327 * @{ 00328 */ 00329 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 00330 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 00331 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 00332 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 00333 /** 00334 * @} 00335 */ 00336 00337 /** @defgroup QSPI_DdrMode QSPI Ddr Mode 00338 * @{ 00339 */ 00340 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 00341 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 00342 /** 00343 * @} 00344 */ 00345 00346 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle 00347 * @{ 00348 */ 00349 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 00350 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/ 00351 /** 00352 * @} 00353 */ 00354 00355 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode 00356 * @{ 00357 */ 00358 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 00359 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup QSPI_MatchMode QSPI Match Mode 00365 * @{ 00366 */ 00367 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 00368 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 00369 /** 00370 * @} 00371 */ 00372 00373 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 00374 * @{ 00375 */ 00376 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 00377 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 00378 /** 00379 * @} 00380 */ 00381 00382 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation 00383 * @{ 00384 */ 00385 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 00386 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 00387 /** 00388 * @} 00389 */ 00390 00391 /** @defgroup QSPI_Flags QSPI Flags 00392 * @{ 00393 */ 00394 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 00395 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 00396 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 00397 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 00398 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 00399 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 00400 /** 00401 * @} 00402 */ 00403 00404 /** @defgroup QSPI_Interrupts QSPI Interrupts 00405 * @{ 00406 */ 00407 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 00408 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 00409 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 00410 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 00411 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 00412 /** 00413 * @} 00414 */ 00415 00416 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 00417 * @{ 00418 */ 00419 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 00420 /** 00421 * @} 00422 */ 00423 00424 /** 00425 * @} 00426 */ 00427 00428 /* Exported macros -----------------------------------------------------------*/ 00429 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 00430 * @{ 00431 */ 00432 00433 /** @brief Reset QSPI handle state 00434 * @param __HANDLE__ QSPI handle. 00435 * @retval None 00436 */ 00437 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 00438 00439 /** @brief Enable QSPI 00440 * @param __HANDLE__ specifies the QSPI Handle. 00441 * @retval None 00442 */ 00443 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00444 00445 /** @brief Disable QSPI 00446 * @param __HANDLE__ specifies the QSPI Handle. 00447 * @retval None 00448 */ 00449 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00450 00451 /** @brief Enables the specified QSPI interrupt. 00452 * @param __HANDLE__ specifies the QSPI Handle. 00453 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. 00454 * This parameter can be one of the following values: 00455 * @arg QSPI_IT_TO: QSPI Time out interrupt 00456 * @arg QSPI_IT_SM: QSPI Status match interrupt 00457 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00458 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00459 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00460 * @retval None 00461 */ 00462 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00463 00464 00465 /** @brief Disables the specified QSPI interrupt. 00466 * @param __HANDLE__ specifies the QSPI Handle. 00467 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. 00468 * This parameter can be one of the following values: 00469 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00470 * @arg QSPI_IT_SM: QSPI Status match interrupt 00471 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00472 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00473 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00474 * @retval None 00475 */ 00476 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00477 00478 /** @brief Checks whether the specified QSPI interrupt source is enabled. 00479 * @param __HANDLE__ specifies the QSPI Handle. 00480 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. 00481 * This parameter can be one of the following values: 00482 * @arg QSPI_IT_TO: QSPI Time out interrupt 00483 * @arg QSPI_IT_SM: QSPI Status match interrupt 00484 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00485 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00486 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00487 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 00488 */ 00489 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 00490 00491 /** 00492 * @brief Get the selected QSPI's flag status. 00493 * @param __HANDLE__ specifies the QSPI Handle. 00494 * @param __FLAG__ specifies the QSPI flag to check. 00495 * This parameter can be one of the following values: 00496 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 00497 * @arg QSPI_FLAG_TO: QSPI Time out flag 00498 * @arg QSPI_FLAG_SM: QSPI Status match flag 00499 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 00500 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00501 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00502 * @retval None 00503 */ 00504 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) 00505 00506 /** @brief Clears the specified QSPI's flag status. 00507 * @param __HANDLE__ specifies the QSPI Handle. 00508 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set 00509 * This parameter can be one of the following values: 00510 * @arg QSPI_FLAG_TO: QSPI Time out flag 00511 * @arg QSPI_FLAG_SM: QSPI Status match flag 00512 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00513 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00514 * @retval None 00515 */ 00516 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 00517 /** 00518 * @} 00519 */ 00520 00521 /* Exported functions --------------------------------------------------------*/ 00522 /** @addtogroup QSPI_Exported_Functions 00523 * @{ 00524 */ 00525 00526 /** @addtogroup QSPI_Exported_Functions_Group1 00527 * @{ 00528 */ 00529 /* Initialization/de-initialization functions ********************************/ 00530 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 00531 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 00532 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 00533 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 00534 /** 00535 * @} 00536 */ 00537 00538 /** @addtogroup QSPI_Exported_Functions_Group2 00539 * @{ 00540 */ 00541 /* IO operation functions *****************************************************/ 00542 /* QSPI IRQ handler method */ 00543 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 00544 00545 /* QSPI indirect mode */ 00546 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 00547 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00548 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00549 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 00550 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00551 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00552 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00553 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00554 00555 /* QSPI status flag polling mode */ 00556 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 00557 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 00558 00559 /* QSPI memory-mapped mode */ 00560 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 00561 /** 00562 * @} 00563 */ 00564 00565 /** @addtogroup QSPI_Exported_Functions_Group3 00566 * @{ 00567 */ 00568 /* Callback functions in non-blocking modes ***********************************/ 00569 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 00570 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 00571 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 00572 00573 /* QSPI indirect mode */ 00574 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 00575 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 00576 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 00577 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 00578 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 00579 00580 /* QSPI status flag polling mode */ 00581 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 00582 00583 /* QSPI memory-mapped mode */ 00584 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 00585 /** 00586 * @} 00587 */ 00588 00589 /** @addtogroup QSPI_Exported_Functions_Group4 00590 * @{ 00591 */ 00592 /* Peripheral Control and State functions ************************************/ 00593 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 00594 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 00595 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 00596 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 00597 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 00598 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 00599 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 00600 /** 00601 * @} 00602 */ 00603 00604 /* Private macros ------------------------------------------------------------*/ 00605 /** @defgroup QSPI_Private_Macros QSPI Private Macros 00606 * @{ 00607 */ 00608 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler 00609 * @{ 00610 */ 00611 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 00612 /** 00613 * @} 00614 */ 00615 00616 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold 00617 * @{ 00618 */ 00619 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) 00620 /** 00621 * @} 00622 */ 00623 00624 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 00625 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 00626 00627 /** @defgroup QSPI_FlashSize QSPI Flash Size 00628 * @{ 00629 */ 00630 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 00631 /** 00632 * @} 00633 */ 00634 00635 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 00636 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 00637 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 00638 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 00639 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 00640 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 00641 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 00642 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 00643 00644 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 00645 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 00646 00647 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \ 00648 ((FLA) == QSPI_FLASH_ID_2)) 00649 00650 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 00651 ((MODE) == QSPI_DUALFLASH_DISABLE)) 00652 00653 00654 /** @defgroup QSPI_Instruction QSPI Instruction 00655 * @{ 00656 */ 00657 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 00658 /** 00659 * @} 00660 */ 00661 00662 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 00663 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 00664 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 00665 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 00666 00667 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 00668 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 00669 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 00670 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 00671 00672 00673 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles 00674 * @{ 00675 */ 00676 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 00677 /** 00678 * @} 00679 */ 00680 00681 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 00682 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 00683 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 00684 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 00685 00686 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 00687 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 00688 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 00689 ((MODE) == QSPI_ADDRESS_4_LINES)) 00690 00691 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 00692 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 00693 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 00694 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 00695 00696 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 00697 ((MODE) == QSPI_DATA_1_LINE) || \ 00698 ((MODE) == QSPI_DATA_2_LINES) || \ 00699 ((MODE) == QSPI_DATA_4_LINES)) 00700 00701 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 00702 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 00703 00704 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 00705 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 00706 00707 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 00708 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 00709 00710 /** @defgroup QSPI_Interval QSPI Interval 00711 * @{ 00712 */ 00713 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 00714 /** 00715 * @} 00716 */ 00717 00718 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size 00719 * @{ 00720 */ 00721 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 00722 /** 00723 * @} 00724 */ 00725 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 00726 ((MODE) == QSPI_MATCH_MODE_OR)) 00727 00728 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 00729 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 00730 00731 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 00732 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 00733 00734 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period 00735 * @{ 00736 */ 00737 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 00738 /** 00739 * @} 00740 */ 00741 00742 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \ 00743 ((FLAG) == QSPI_FLAG_TO) || \ 00744 ((FLAG) == QSPI_FLAG_SM) || \ 00745 ((FLAG) == QSPI_FLAG_FT) || \ 00746 ((FLAG) == QSPI_FLAG_TC) || \ 00747 ((FLAG) == QSPI_FLAG_TE)) 00748 00749 #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U)) 00750 /** 00751 * @} 00752 */ 00753 00754 /* Private functions ---------------------------------------------------------*/ 00755 /** @defgroup QSPI_Private_Functions QSPI Private Functions 00756 * @{ 00757 */ 00758 00759 /** 00760 * @} 00761 */ 00762 00763 /** 00764 * @} 00765 */ 00766 00767 /** 00768 * @} 00769 */ 00770 00771 /** 00772 * @} 00773 */ 00774 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || 00775 STM32F413xx || STM32F423xx */ 00776 00777 #ifdef __cplusplus 00778 } 00779 #endif 00780 00781 #endif /* __STM32F4xx_HAL_QSPI_H */ 00782 00783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1