|
STM32F439xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dsi.h 00004 * @author MCD Application Team 00005 * @brief Header file of DSI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_HAL_DSI_H 00038 #define __STM32F4xx_HAL_DSI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined(DSI) 00045 /* Includes ------------------------------------------------------------------*/ 00046 #include "stm32f4xx_hal_def.h" 00047 00048 /** @addtogroup STM32F4xx_HAL_Driver 00049 * @{ 00050 */ 00051 00052 /** @defgroup DSI DSI 00053 * @brief DSI HAL module driver 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** 00059 * @brief DSI Init Structure definition 00060 */ 00061 typedef struct 00062 { 00063 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control 00064 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ 00065 00066 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division 00067 The values 0 and 1 stop the TX_ESC clock generation */ 00068 00069 uint32_t NumberOfLanes; /*!< Number of lanes 00070 This parameter can be any value of @ref DSI_Number_Of_Lanes */ 00071 00072 }DSI_InitTypeDef; 00073 00074 /** 00075 * @brief DSI PLL Clock structure definition 00076 */ 00077 typedef struct 00078 { 00079 uint32_t PLLNDIV; /*!< PLL Loop Division Factor 00080 This parameter must be a value between 10 and 125 */ 00081 00082 uint32_t PLLIDF; /*!< PLL Input Division Factor 00083 This parameter can be any value of @ref DSI_PLL_IDF */ 00084 00085 uint32_t PLLODF; /*!< PLL Output Division Factor 00086 This parameter can be any value of @ref DSI_PLL_ODF */ 00087 00088 }DSI_PLLInitTypeDef; 00089 00090 /** 00091 * @brief DSI Video mode configuration 00092 */ 00093 typedef struct 00094 { 00095 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 00096 00097 uint32_t ColorCoding; /*!< Color coding for LTDC interface 00098 This parameter can be any value of @ref DSI_Color_Coding */ 00099 00100 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using 00101 18-bit configuration). 00102 This parameter can be any value of @ref DSI_LooselyPacked */ 00103 00104 uint32_t Mode; /*!< Video mode type 00105 This parameter can be any value of @ref DSI_Video_Mode_Type */ 00106 00107 uint32_t PacketSize; /*!< Video packet size */ 00108 00109 uint32_t NumberOfChunks; /*!< Number of chunks */ 00110 00111 uint32_t NullPacketSize; /*!< Null packet size */ 00112 00113 uint32_t HSPolarity; /*!< HSYNC pin polarity 00114 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 00115 00116 uint32_t VSPolarity; /*!< VSYNC pin polarity 00117 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 00118 00119 uint32_t DEPolarity; /*!< Data Enable pin polarity 00120 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 00121 00122 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ 00123 00124 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ 00125 00126 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ 00127 00128 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ 00129 00130 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ 00131 00132 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ 00133 00134 uint32_t VerticalActive; /*!< Vertical active duration */ 00135 00136 uint32_t LPCommandEnable; /*!< Low-power command enable 00137 This parameter can be any value of @ref DSI_LP_Command */ 00138 00139 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 00140 can fit in a line during VSA, VBP and VFP regions */ 00141 00142 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 00143 can fit in a line during VACT region */ 00144 00145 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable 00146 This parameter can be any value of @ref DSI_LP_HFP */ 00147 00148 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable 00149 This parameter can be any value of @ref DSI_LP_HBP */ 00150 00151 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable 00152 This parameter can be any value of @ref DSI_LP_VACT */ 00153 00154 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable 00155 This parameter can be any value of @ref DSI_LP_VFP */ 00156 00157 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable 00158 This parameter can be any value of @ref DSI_LP_VBP */ 00159 00160 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable 00161 This parameter can be any value of @ref DSI_LP_VSYNC */ 00162 00163 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable 00164 This parameter can be any value of @ref DSI_FBTA_acknowledge */ 00165 00166 }DSI_VidCfgTypeDef; 00167 00168 /** 00169 * @brief DSI Adapted command mode configuration 00170 */ 00171 typedef struct 00172 { 00173 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 00174 00175 uint32_t ColorCoding; /*!< Color coding for LTDC interface 00176 This parameter can be any value of @ref DSI_Color_Coding */ 00177 00178 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in 00179 pixels. This parameter can be any value between 0x00 and 0xFFFFU */ 00180 00181 uint32_t TearingEffectSource; /*!< Tearing effect source 00182 This parameter can be any value of @ref DSI_TearingEffectSource */ 00183 00184 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity 00185 This parameter can be any value of @ref DSI_TearingEffectPolarity */ 00186 00187 uint32_t HSPolarity; /*!< HSYNC pin polarity 00188 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 00189 00190 uint32_t VSPolarity; /*!< VSYNC pin polarity 00191 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 00192 00193 uint32_t DEPolarity; /*!< Data Enable pin polarity 00194 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 00195 00196 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted 00197 This parameter can be any value of @ref DSI_Vsync_Polarity */ 00198 00199 uint32_t AutomaticRefresh; /*!< Automatic refresh mode 00200 This parameter can be any value of @ref DSI_AutomaticRefresh */ 00201 00202 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable 00203 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ 00204 00205 }DSI_CmdCfgTypeDef; 00206 00207 /** 00208 * @brief DSI command transmission mode configuration 00209 */ 00210 typedef struct 00211 { 00212 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission 00213 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ 00214 00215 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission 00216 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ 00217 00218 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission 00219 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ 00220 00221 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission 00222 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ 00223 00224 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission 00225 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ 00226 00227 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission 00228 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ 00229 00230 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission 00231 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ 00232 00233 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission 00234 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ 00235 00236 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission 00237 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ 00238 00239 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission 00240 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ 00241 00242 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission 00243 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ 00244 00245 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission 00246 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ 00247 00248 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable 00249 This parameter can be any value of @ref DSI_AcknowledgeRequest */ 00250 00251 }DSI_LPCmdTypeDef; 00252 00253 /** 00254 * @brief DSI PHY Timings definition 00255 */ 00256 typedef struct 00257 { 00258 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed 00259 to low-power transmission */ 00260 00261 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power 00262 to high-speed transmission */ 00263 00264 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed 00265 to low-power transmission */ 00266 00267 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power 00268 to high-speed transmission */ 00269 00270 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ 00271 00272 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the 00273 Stop state */ 00274 00275 }DSI_PHY_TimerTypeDef; 00276 00277 /** 00278 * @brief DSI HOST Timeouts definition 00279 */ 00280 typedef struct 00281 { 00282 uint32_t TimeoutCkdiv; /*!< Time-out clock division */ 00283 00284 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ 00285 00286 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ 00287 00288 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ 00289 00290 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ 00291 00292 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ 00293 00294 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode 00295 This parameter can be any value of @ref DSI_HS_PrespMode */ 00296 00297 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ 00298 00299 uint32_t BTATimeout; /*!< BTA time-out */ 00300 00301 }DSI_HOST_TimeoutTypeDef; 00302 00303 /** 00304 * @brief DSI States Structure definition 00305 */ 00306 typedef enum 00307 { 00308 HAL_DSI_STATE_RESET = 0x00U, 00309 HAL_DSI_STATE_READY = 0x01U, 00310 HAL_DSI_STATE_ERROR = 0x02U, 00311 HAL_DSI_STATE_BUSY = 0x03U, 00312 HAL_DSI_STATE_TIMEOUT = 0x04U 00313 }HAL_DSI_StateTypeDef; 00314 00315 /** 00316 * @brief DSI Handle Structure definition 00317 */ 00318 typedef struct 00319 { 00320 DSI_TypeDef *Instance; /*!< Register base address */ 00321 DSI_InitTypeDef Init; /*!< DSI required parameters */ 00322 HAL_LockTypeDef Lock; /*!< DSI peripheral status */ 00323 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ 00324 __IO uint32_t ErrorCode; /*!< DSI Error code */ 00325 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ 00326 }DSI_HandleTypeDef; 00327 00328 /* Exported constants --------------------------------------------------------*/ 00329 /** @defgroup DSI_DCS_Command DSI DCS Command 00330 * @{ 00331 */ 00332 #define DSI_ENTER_IDLE_MODE 0x39U 00333 #define DSI_ENTER_INVERT_MODE 0x21U 00334 #define DSI_ENTER_NORMAL_MODE 0x13U 00335 #define DSI_ENTER_PARTIAL_MODE 0x12U 00336 #define DSI_ENTER_SLEEP_MODE 0x10U 00337 #define DSI_EXIT_IDLE_MODE 0x38U 00338 #define DSI_EXIT_INVERT_MODE 0x20U 00339 #define DSI_EXIT_SLEEP_MODE 0x11U 00340 #define DSI_GET_3D_CONTROL 0x3FU 00341 #define DSI_GET_ADDRESS_MODE 0x0BU 00342 #define DSI_GET_BLUE_CHANNEL 0x08U 00343 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU 00344 #define DSI_GET_DISPLAY_MODE 0x0DU 00345 #define DSI_GET_GREEN_CHANNEL 0x07U 00346 #define DSI_GET_PIXEL_FORMAT 0x0CU 00347 #define DSI_GET_POWER_MODE 0x0AU 00348 #define DSI_GET_RED_CHANNEL 0x06U 00349 #define DSI_GET_SCANLINE 0x45U 00350 #define DSI_GET_SIGNAL_MODE 0x0EU 00351 #define DSI_NOP 0x00U 00352 #define DSI_READ_DDB_CONTINUE 0xA8U 00353 #define DSI_READ_DDB_START 0xA1U 00354 #define DSI_READ_MEMORY_CONTINUE 0x3EU 00355 #define DSI_READ_MEMORY_START 0x2EU 00356 #define DSI_SET_3D_CONTROL 0x3DU 00357 #define DSI_SET_ADDRESS_MODE 0x36U 00358 #define DSI_SET_COLUMN_ADDRESS 0x2AU 00359 #define DSI_SET_DISPLAY_OFF 0x28U 00360 #define DSI_SET_DISPLAY_ON 0x29U 00361 #define DSI_SET_GAMMA_CURVE 0x26U 00362 #define DSI_SET_PAGE_ADDRESS 0x2BU 00363 #define DSI_SET_PARTIAL_COLUMNS 0x31U 00364 #define DSI_SET_PARTIAL_ROWS 0x30U 00365 #define DSI_SET_PIXEL_FORMAT 0x3AU 00366 #define DSI_SET_SCROLL_AREA 0x33U 00367 #define DSI_SET_SCROLL_START 0x37U 00368 #define DSI_SET_TEAR_OFF 0x34U 00369 #define DSI_SET_TEAR_ON 0x35U 00370 #define DSI_SET_TEAR_SCANLINE 0x44U 00371 #define DSI_SET_VSYNC_TIMING 0x40U 00372 #define DSI_SOFT_RESET 0x01U 00373 #define DSI_WRITE_LUT 0x2DU 00374 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU 00375 #define DSI_WRITE_MEMORY_START 0x2CU 00376 /** 00377 * @} 00378 */ 00379 00380 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type 00381 * @{ 00382 */ 00383 #define DSI_VID_MODE_NB_PULSES 0U 00384 #define DSI_VID_MODE_NB_EVENTS 1U 00385 #define DSI_VID_MODE_BURST 2U 00386 /** 00387 * @} 00388 */ 00389 00390 /** @defgroup DSI_Color_Mode DSI Color Mode 00391 * @{ 00392 */ 00393 #define DSI_COLOR_MODE_FULL 0x00000000U 00394 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM 00395 /** 00396 * @} 00397 */ 00398 00399 /** @defgroup DSI_ShutDown DSI ShutDown 00400 * @{ 00401 */ 00402 #define DSI_DISPLAY_ON 0x00000000U 00403 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN 00404 /** 00405 * @} 00406 */ 00407 00408 /** @defgroup DSI_LP_Command DSI LP Command 00409 * @{ 00410 */ 00411 #define DSI_LP_COMMAND_DISABLE 0x00000000U 00412 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE 00413 /** 00414 * @} 00415 */ 00416 00417 /** @defgroup DSI_LP_HFP DSI LP HFP 00418 * @{ 00419 */ 00420 #define DSI_LP_HFP_DISABLE 0x00000000U 00421 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE 00422 /** 00423 * @} 00424 */ 00425 00426 /** @defgroup DSI_LP_HBP DSI LP HBP 00427 * @{ 00428 */ 00429 #define DSI_LP_HBP_DISABLE 0x00000000U 00430 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE 00431 /** 00432 * @} 00433 */ 00434 00435 /** @defgroup DSI_LP_VACT DSI LP VACT 00436 * @{ 00437 */ 00438 #define DSI_LP_VACT_DISABLE 0x00000000U 00439 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE 00440 /** 00441 * @} 00442 */ 00443 00444 /** @defgroup DSI_LP_VFP DSI LP VFP 00445 * @{ 00446 */ 00447 #define DSI_LP_VFP_DISABLE 0x00000000U 00448 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE 00449 /** 00450 * @} 00451 */ 00452 00453 /** @defgroup DSI_LP_VBP DSI LP VBP 00454 * @{ 00455 */ 00456 #define DSI_LP_VBP_DISABLE 0x00000000U 00457 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE 00458 /** 00459 * @} 00460 */ 00461 00462 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC 00463 * @{ 00464 */ 00465 #define DSI_LP_VSYNC_DISABLE 0x00000000U 00466 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE 00467 /** 00468 * @} 00469 */ 00470 00471 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge 00472 * @{ 00473 */ 00474 #define DSI_FBTAA_DISABLE 0x00000000U 00475 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE 00476 /** 00477 * @} 00478 */ 00479 00480 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source 00481 * @{ 00482 */ 00483 #define DSI_TE_DSILINK 0x00000000U 00484 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC 00485 /** 00486 * @} 00487 */ 00488 00489 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity 00490 * @{ 00491 */ 00492 #define DSI_TE_RISING_EDGE 0x00000000U 00493 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL 00494 /** 00495 * @} 00496 */ 00497 00498 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity 00499 * @{ 00500 */ 00501 #define DSI_VSYNC_FALLING 0x00000000U 00502 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL 00503 /** 00504 * @} 00505 */ 00506 00507 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh 00508 * @{ 00509 */ 00510 #define DSI_AR_DISABLE 0x00000000U 00511 #define DSI_AR_ENABLE DSI_WCFGR_AR 00512 /** 00513 * @} 00514 */ 00515 00516 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request 00517 * @{ 00518 */ 00519 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U 00520 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE 00521 /** 00522 * @} 00523 */ 00524 00525 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request 00526 * @{ 00527 */ 00528 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U 00529 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE 00530 /** 00531 * @} 00532 */ 00533 00534 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP 00535 * @{ 00536 */ 00537 #define DSI_LP_GSW0P_DISABLE 0x00000000U 00538 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX 00539 /** 00540 * @} 00541 */ 00542 00543 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP 00544 * @{ 00545 */ 00546 #define DSI_LP_GSW1P_DISABLE 0x00000000U 00547 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX 00548 /** 00549 * @} 00550 */ 00551 00552 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP 00553 * @{ 00554 */ 00555 #define DSI_LP_GSW2P_DISABLE 0x00000000U 00556 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX 00557 /** 00558 * @} 00559 */ 00560 00561 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP 00562 * @{ 00563 */ 00564 #define DSI_LP_GSR0P_DISABLE 0x00000000U 00565 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX 00566 /** 00567 * @} 00568 */ 00569 00570 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP 00571 * @{ 00572 */ 00573 #define DSI_LP_GSR1P_DISABLE 0x00000000U 00574 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX 00575 /** 00576 * @} 00577 */ 00578 00579 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP 00580 * @{ 00581 */ 00582 #define DSI_LP_GSR2P_DISABLE 0x00000000U 00583 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX 00584 /** 00585 * @} 00586 */ 00587 00588 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite 00589 * @{ 00590 */ 00591 #define DSI_LP_GLW_DISABLE 0x00000000U 00592 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX 00593 /** 00594 * @} 00595 */ 00596 00597 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP 00598 * @{ 00599 */ 00600 #define DSI_LP_DSW0P_DISABLE 0x00000000U 00601 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX 00602 /** 00603 * @} 00604 */ 00605 00606 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP 00607 * @{ 00608 */ 00609 #define DSI_LP_DSW1P_DISABLE 0x00000000U 00610 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX 00611 /** 00612 * @} 00613 */ 00614 00615 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP 00616 * @{ 00617 */ 00618 #define DSI_LP_DSR0P_DISABLE 0x00000000U 00619 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX 00620 /** 00621 * @} 00622 */ 00623 00624 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write 00625 * @{ 00626 */ 00627 #define DSI_LP_DLW_DISABLE 0x00000000U 00628 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX 00629 /** 00630 * @} 00631 */ 00632 00633 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet 00634 * @{ 00635 */ 00636 #define DSI_LP_MRDP_DISABLE 0x00000000U 00637 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS 00638 /** 00639 * @} 00640 */ 00641 00642 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode 00643 * @{ 00644 */ 00645 #define DSI_HS_PM_DISABLE 0x00000000U 00646 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM 00647 /** 00648 * @} 00649 */ 00650 00651 00652 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control 00653 * @{ 00654 */ 00655 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U 00656 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR 00657 /** 00658 * @} 00659 */ 00660 00661 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes 00662 * @{ 00663 */ 00664 #define DSI_ONE_DATA_LANE 0U 00665 #define DSI_TWO_DATA_LANES 1U 00666 /** 00667 * @} 00668 */ 00669 00670 /** @defgroup DSI_FlowControl DSI Flow Control 00671 * @{ 00672 */ 00673 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE 00674 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE 00675 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE 00676 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE 00677 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE 00678 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ 00679 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ 00680 DSI_FLOW_CONTROL_EOTP_TX) 00681 /** 00682 * @} 00683 */ 00684 00685 /** @defgroup DSI_Color_Coding DSI Color Coding 00686 * @{ 00687 */ 00688 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ 00689 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ 00690 #define DSI_RGB888 0x00000005U 00691 /** 00692 * @} 00693 */ 00694 00695 /** @defgroup DSI_LooselyPacked DSI Loosely Packed 00696 * @{ 00697 */ 00698 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE 00699 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U 00700 /** 00701 * @} 00702 */ 00703 00704 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity 00705 * @{ 00706 */ 00707 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U 00708 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP 00709 /** 00710 * @} 00711 */ 00712 00713 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity 00714 * @{ 00715 */ 00716 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U 00717 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP 00718 /** 00719 * @} 00720 */ 00721 00722 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity 00723 * @{ 00724 */ 00725 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U 00726 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP 00727 /** 00728 * @} 00729 */ 00730 00731 /** @defgroup DSI_PLL_IDF DSI PLL IDF 00732 * @{ 00733 */ 00734 #define DSI_PLL_IN_DIV1 0x00000001U 00735 #define DSI_PLL_IN_DIV2 0x00000002U 00736 #define DSI_PLL_IN_DIV3 0x00000003U 00737 #define DSI_PLL_IN_DIV4 0x00000004U 00738 #define DSI_PLL_IN_DIV5 0x00000005U 00739 #define DSI_PLL_IN_DIV6 0x00000006U 00740 #define DSI_PLL_IN_DIV7 0x00000007U 00741 /** 00742 * @} 00743 */ 00744 00745 /** @defgroup DSI_PLL_ODF DSI PLL ODF 00746 * @{ 00747 */ 00748 #define DSI_PLL_OUT_DIV1 0x00000000U 00749 #define DSI_PLL_OUT_DIV2 0x00000001U 00750 #define DSI_PLL_OUT_DIV4 0x00000002U 00751 #define DSI_PLL_OUT_DIV8 0x00000003U 00752 /** 00753 * @} 00754 */ 00755 00756 /** @defgroup DSI_Flags DSI Flags 00757 * @{ 00758 */ 00759 #define DSI_FLAG_TE DSI_WISR_TEIF 00760 #define DSI_FLAG_ER DSI_WISR_ERIF 00761 #define DSI_FLAG_BUSY DSI_WISR_BUSY 00762 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS 00763 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF 00764 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF 00765 #define DSI_FLAG_RRS DSI_WISR_RRS 00766 #define DSI_FLAG_RR DSI_WISR_RRIF 00767 /** 00768 * @} 00769 */ 00770 00771 /** @defgroup DSI_Interrupts DSI Interrupts 00772 * @{ 00773 */ 00774 #define DSI_IT_TE DSI_WIER_TEIE 00775 #define DSI_IT_ER DSI_WIER_ERIE 00776 #define DSI_IT_PLLL DSI_WIER_PLLLIE 00777 #define DSI_IT_PLLU DSI_WIER_PLLUIE 00778 #define DSI_IT_RR DSI_WIER_RRIE 00779 /** 00780 * @} 00781 */ 00782 00783 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type 00784 * @{ 00785 */ 00786 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ 00787 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ 00788 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ 00789 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ 00790 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ 00791 /** 00792 * @} 00793 */ 00794 00795 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type 00796 * @{ 00797 */ 00798 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ 00799 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ 00800 /** 00801 * @} 00802 */ 00803 00804 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type 00805 * @{ 00806 */ 00807 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ 00808 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ 00809 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ 00810 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ 00811 /** 00812 * @} 00813 */ 00814 00815 /** @defgroup DSI_Error_Data_Type DSI Error Data Type 00816 * @{ 00817 */ 00818 #define HAL_DSI_ERROR_NONE 0U 00819 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ 00820 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ 00821 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ 00822 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ 00823 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ 00824 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ 00825 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ 00826 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ 00827 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ 00828 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ 00829 /** 00830 * @} 00831 */ 00832 00833 /** @defgroup DSI_Lane_Group DSI Lane Group 00834 * @{ 00835 */ 00836 #define DSI_CLOCK_LANE 0x00000000U 00837 #define DSI_DATA_LANES 0x00000001U 00838 /** 00839 * @} 00840 */ 00841 00842 /** @defgroup DSI_Communication_Delay DSI Communication Delay 00843 * @{ 00844 */ 00845 #define DSI_SLEW_RATE_HSTX 0x00000000U 00846 #define DSI_SLEW_RATE_LPTX 0x00000001U 00847 #define DSI_HS_DELAY 0x00000002U 00848 /** 00849 * @} 00850 */ 00851 00852 /** @defgroup DSI_CustomLane DSI CustomLane 00853 * @{ 00854 */ 00855 #define DSI_SWAP_LANE_PINS 0x00000000U 00856 #define DSI_INVERT_HS_SIGNAL 0x00000001U 00857 /** 00858 * @} 00859 */ 00860 00861 /** @defgroup DSI_Lane_Select DSI Lane Select 00862 * @{ 00863 */ 00864 #define DSI_CLK_LANE 0x00000000U 00865 #define DSI_DATA_LANE0 0x00000001U 00866 #define DSI_DATA_LANE1 0x00000002U 00867 /** 00868 * @} 00869 */ 00870 00871 /** @defgroup DSI_PHY_Timing DSI PHY Timing 00872 * @{ 00873 */ 00874 #define DSI_TCLK_POST 0x00000000U 00875 #define DSI_TLPX_CLK 0x00000001U 00876 #define DSI_THS_EXIT 0x00000002U 00877 #define DSI_TLPX_DATA 0x00000003U 00878 #define DSI_THS_ZERO 0x00000004U 00879 #define DSI_THS_TRAIL 0x00000005U 00880 #define DSI_THS_PREPARE 0x00000006U 00881 #define DSI_TCLK_ZERO 0x00000007U 00882 #define DSI_TCLK_PREPARE 0x00000008U 00883 /** 00884 * @} 00885 */ 00886 00887 /* Exported macros -----------------------------------------------------------*/ 00888 /** 00889 * @brief Enables the DSI host. 00890 * @param __HANDLE__ DSI handle 00891 * @retval None. 00892 */ 00893 #define __HAL_DSI_ENABLE(__HANDLE__) do { \ 00894 __IO uint32_t tmpreg = 0x00U; \ 00895 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00896 /* Delay after an DSI Host enabling */ \ 00897 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00898 UNUSED(tmpreg); \ 00899 }while(0U) 00900 00901 /** 00902 * @brief Disables the DSI host. 00903 * @param __HANDLE__ DSI handle 00904 * @retval None. 00905 */ 00906 #define __HAL_DSI_DISABLE(__HANDLE__) do { \ 00907 __IO uint32_t tmpreg = 0x00U; \ 00908 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00909 /* Delay after an DSI Host disabling */ \ 00910 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00911 UNUSED(tmpreg); \ 00912 }while(0U) 00913 00914 /** 00915 * @brief Enables the DSI wrapper. 00916 * @param __HANDLE__ DSI handle 00917 * @retval None. 00918 */ 00919 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ 00920 __IO uint32_t tmpreg = 0x00U; \ 00921 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00922 /* Delay after an DSI warpper enabling */ \ 00923 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00924 UNUSED(tmpreg); \ 00925 }while(0U) 00926 00927 /** 00928 * @brief Disable the DSI wrapper. 00929 * @param __HANDLE__ DSI handle 00930 * @retval None. 00931 */ 00932 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ 00933 __IO uint32_t tmpreg = 0x00U; \ 00934 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00935 /* Delay after an DSI warpper disabling*/ \ 00936 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00937 UNUSED(tmpreg); \ 00938 }while(0U) 00939 00940 /** 00941 * @brief Enables the DSI PLL. 00942 * @param __HANDLE__ DSI handle 00943 * @retval None. 00944 */ 00945 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ 00946 __IO uint32_t tmpreg = 0x00U; \ 00947 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 00948 /* Delay after an DSI PLL enabling */ \ 00949 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 00950 UNUSED(tmpreg); \ 00951 }while(0U) 00952 00953 /** 00954 * @brief Disables the DSI PLL. 00955 * @param __HANDLE__ DSI handle 00956 * @retval None. 00957 */ 00958 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ 00959 __IO uint32_t tmpreg = 0x00U; \ 00960 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 00961 /* Delay after an DSI PLL disabling */ \ 00962 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 00963 UNUSED(tmpreg); \ 00964 }while(0U) 00965 00966 /** 00967 * @brief Enables the DSI regulator. 00968 * @param __HANDLE__ DSI handle 00969 * @retval None. 00970 */ 00971 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ 00972 __IO uint32_t tmpreg = 0x00U; \ 00973 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 00974 /* Delay after an DSI regulator enabling */ \ 00975 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 00976 UNUSED(tmpreg); \ 00977 }while(0U) 00978 00979 /** 00980 * @brief Disables the DSI regulator. 00981 * @param __HANDLE__ DSI handle 00982 * @retval None. 00983 */ 00984 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ 00985 __IO uint32_t tmpreg = 0x00U; \ 00986 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 00987 /* Delay after an DSI regulator disabling */ \ 00988 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 00989 UNUSED(tmpreg); \ 00990 }while(0U) 00991 00992 /** 00993 * @brief Get the DSI pending flags. 00994 * @param __HANDLE__ DSI handle. 00995 * @param __FLAG__ Get the specified flag. 00996 * This parameter can be any combination of the following values: 00997 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 00998 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 00999 * @arg DSI_FLAG_BUSY : Busy Flag 01000 * @arg DSI_FLAG_PLLLS: PLL Lock Status 01001 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 01002 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 01003 * @arg DSI_FLAG_RRS : Regulator Ready Flag 01004 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 01005 * @retval The state of FLAG (SET or RESET). 01006 */ 01007 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) 01008 01009 /** 01010 * @brief Clears the DSI pending flags. 01011 * @param __HANDLE__ DSI handle. 01012 * @param __FLAG__ specifies the flag to clear. 01013 * This parameter can be any combination of the following values: 01014 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 01015 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 01016 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 01017 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 01018 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 01019 * @retval None 01020 */ 01021 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) 01022 01023 /** 01024 * @brief Enables the specified DSI interrupts. 01025 * @param __HANDLE__ DSI handle. 01026 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. 01027 * This parameter can be any combination of the following values: 01028 * @arg DSI_IT_TE : Tearing Effect Interrupt 01029 * @arg DSI_IT_ER : End of Refresh Interrupt 01030 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01031 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01032 * @arg DSI_IT_RR : Regulator Ready Interrupt 01033 * @retval None 01034 */ 01035 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) 01036 01037 /** 01038 * @brief Disables the specified DSI interrupts. 01039 * @param __HANDLE__ DSI handle 01040 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. 01041 * This parameter can be any combination of the following values: 01042 * @arg DSI_IT_TE : Tearing Effect Interrupt 01043 * @arg DSI_IT_ER : End of Refresh Interrupt 01044 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01045 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01046 * @arg DSI_IT_RR : Regulator Ready Interrupt 01047 * @retval None 01048 */ 01049 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) 01050 01051 /** 01052 * @brief Checks whether the specified DSI interrupt source is enabled or not. 01053 * @param __HANDLE__ DSI handle 01054 * @param __INTERRUPT__ specifies the DSI interrupt source to check. 01055 * This parameter can be one of the following values: 01056 * @arg DSI_IT_TE : Tearing Effect Interrupt 01057 * @arg DSI_IT_ER : End of Refresh Interrupt 01058 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01059 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01060 * @arg DSI_IT_RR : Regulator Ready Interrupt 01061 * @retval The state of INTERRUPT (SET or RESET). 01062 */ 01063 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) 01064 01065 /* Exported functions --------------------------------------------------------*/ 01066 /** @defgroup DSI_Exported_Functions DSI Exported Functions 01067 * @{ 01068 */ 01069 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); 01070 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); 01071 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); 01072 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); 01073 01074 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); 01075 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); 01076 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); 01077 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); 01078 01079 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); 01080 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); 01081 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); 01082 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); 01083 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); 01084 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); 01085 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); 01086 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); 01087 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); 01088 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); 01089 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); 01090 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); 01091 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 01092 uint32_t ChannelID, 01093 uint32_t Mode, 01094 uint32_t Param1, 01095 uint32_t Param2); 01096 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 01097 uint32_t ChannelID, 01098 uint32_t Mode, 01099 uint32_t NbParams, 01100 uint32_t Param1, 01101 uint8_t* ParametersTable); 01102 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 01103 uint32_t ChannelNbr, 01104 uint8_t* Array, 01105 uint32_t Size, 01106 uint32_t Mode, 01107 uint32_t DCSCmd, 01108 uint8_t* ParametersTable); 01109 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); 01110 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); 01111 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); 01112 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); 01113 01114 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); 01115 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); 01116 01117 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value); 01118 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); 01119 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); 01120 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State); 01121 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value); 01122 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); 01123 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); 01124 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); 01125 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); 01126 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); 01127 01128 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); 01129 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); 01130 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); 01131 /** 01132 * @} 01133 */ 01134 01135 /* Private types -------------------------------------------------------------*/ 01136 /** @defgroup DSI_Private_Types DSI Private Types 01137 * @{ 01138 */ 01139 01140 /** 01141 * @} 01142 */ 01143 01144 /* Private defines -----------------------------------------------------------*/ 01145 /** @defgroup DSI_Private_Defines DSI Private Defines 01146 * @{ 01147 */ 01148 01149 /** 01150 * @} 01151 */ 01152 01153 /* Private variables ---------------------------------------------------------*/ 01154 /** @defgroup DSI_Private_Variables DSI Private Variables 01155 * @{ 01156 */ 01157 01158 /** 01159 * @} 01160 */ 01161 01162 /* Private constants ---------------------------------------------------------*/ 01163 /** @defgroup DSI_Private_Constants DSI Private Constants 01164 * @{ 01165 */ 01166 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ 01167 /** 01168 * @} 01169 */ 01170 01171 /* Private macros ------------------------------------------------------------*/ 01172 /** @defgroup DSI_Private_Macros DSI Private Macros 01173 * @{ 01174 */ 01175 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) 01176 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ 01177 ((IDF) == DSI_PLL_IN_DIV2) || \ 01178 ((IDF) == DSI_PLL_IN_DIV3) || \ 01179 ((IDF) == DSI_PLL_IN_DIV4) || \ 01180 ((IDF) == DSI_PLL_IN_DIV5) || \ 01181 ((IDF) == DSI_PLL_IN_DIV6) || \ 01182 ((IDF) == DSI_PLL_IN_DIV7)) 01183 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ 01184 ((ODF) == DSI_PLL_OUT_DIV2) || \ 01185 ((ODF) == DSI_PLL_OUT_DIV4) || \ 01186 ((ODF) == DSI_PLL_OUT_DIV8)) 01187 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) 01188 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) 01189 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) 01190 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) 01191 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) 01192 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) 01193 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) 01194 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) 01195 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ 01196 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ 01197 ((VideoModeType) == DSI_VID_MODE_BURST)) 01198 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) 01199 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) 01200 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) 01201 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) 01202 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) 01203 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) 01204 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) 01205 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) 01206 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) 01207 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) 01208 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) 01209 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) 01210 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) 01211 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) 01212 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) 01213 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) 01214 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) 01215 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) 01216 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) 01217 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) 01218 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) 01219 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) 01220 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) 01221 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) 01222 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) 01223 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) 01224 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) 01225 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) 01226 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ 01227 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ 01228 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ 01229 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ 01230 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) 01231 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ 01232 ((MODE) == DSI_GEN_LONG_PKT_WRITE)) 01233 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ 01234 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ 01235 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ 01236 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) 01237 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) 01238 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) 01239 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) 01240 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) 01241 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ 01242 ((Timing) == DSI_TLPX_CLK ) || \ 01243 ((Timing) == DSI_THS_EXIT ) || \ 01244 ((Timing) == DSI_TLPX_DATA ) || \ 01245 ((Timing) == DSI_THS_ZERO ) || \ 01246 ((Timing) == DSI_THS_TRAIL ) || \ 01247 ((Timing) == DSI_THS_PREPARE ) || \ 01248 ((Timing) == DSI_TCLK_ZERO ) || \ 01249 ((Timing) == DSI_TCLK_PREPARE)) 01250 01251 /** 01252 * @} 01253 */ 01254 01255 /* Private functions prototypes ----------------------------------------------*/ 01256 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes 01257 * @{ 01258 */ 01259 01260 /** 01261 * @} 01262 */ 01263 01264 /* Private functions ---------------------------------------------------------*/ 01265 /** @defgroup DSI_Private_Functions DSI Private Functions 01266 * @{ 01267 */ 01268 01269 /** 01270 * @} 01271 */ 01272 01273 /** 01274 * @} 01275 */ 01276 01277 /** 01278 * @} 01279 */ 01280 #endif /* DSI */ 01281 01282 #ifdef __cplusplus 01283 } 01284 #endif 01285 01286 #endif /* __STM32F4xx_HAL_DSI_H */ 01287 01288 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1