STM32F439xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dsi.c 00004 * @author MCD Application Team 00005 * @brief DSI HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the DSI peripheral: 00008 * + Initialization and de-initialization functions 00009 * + IO operation functions 00010 * + Peripheral Control functions 00011 * + Peripheral State and Errors functions 00012 ****************************************************************************** 00013 * @attention 00014 * 00015 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00016 * 00017 * Redistribution and use in source and binary forms, with or without modification, 00018 * are permitted provided that the following conditions are met: 00019 * 1. Redistributions of source code must retain the above copyright notice, 00020 * this list of conditions and the following disclaimer. 00021 * 2. Redistributions in binary form must reproduce the above copyright notice, 00022 * this list of conditions and the following disclaimer in the documentation 00023 * and/or other materials provided with the distribution. 00024 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00025 * may be used to endorse or promote products derived from this software 00026 * without specific prior written permission. 00027 * 00028 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00029 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00030 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00031 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00032 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00033 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00034 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00036 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00037 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00038 * 00039 ****************************************************************************** 00040 */ 00041 00042 /* Includes ------------------------------------------------------------------*/ 00043 #include "stm32f4xx_hal.h" 00044 00045 /** @addtogroup STM32F4xx_HAL_Driver 00046 * @{ 00047 */ 00048 00049 #ifdef HAL_DSI_MODULE_ENABLED 00050 00051 #if defined(DSI) 00052 00053 /** @addtogroup DSI 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private defines -----------------------------------------------------------*/ 00059 /** @addtogroup DSI_Private_Constants 00060 * @{ 00061 */ 00062 #define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */ 00063 00064 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ 00065 DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ 00066 DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ 00067 DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) 00068 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) 00069 #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX 00070 #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX 00071 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) 00072 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE 00073 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE 00074 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE 00075 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE 00076 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) 00077 /** 00078 * @} 00079 */ 00080 00081 /* Private variables ---------------------------------------------------------*/ 00082 /* Private constants ---------------------------------------------------------*/ 00083 /* Private macros ------------------------------------------------------------*/ 00084 /* Private function prototypes -----------------------------------------------*/ 00085 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1); 00086 00087 /* Private functions ---------------------------------------------------------*/ 00088 /** 00089 * @brief Generic DSI packet header configuration 00090 * @param DSIx Pointer to DSI register base 00091 * @param ChannelID Virtual channel ID of the header packet 00092 * @param DataType Packet data type of the header packet 00093 * This parameter can be any value of : 00094 * @ref DSI_SHORT_WRITE_PKT_Data_Type 00095 * or @ref DSI_LONG_WRITE_PKT_Data_Type 00096 * or @ref DSI_SHORT_READ_PKT_Data_Type 00097 * or DSI_MAX_RETURN_PKT_SIZE 00098 * @param Data0 Word count LSB 00099 * @param Data1 Word count MSB 00100 * @retval None 00101 */ 00102 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, 00103 uint32_t ChannelID, 00104 uint32_t DataType, 00105 uint32_t Data0, 00106 uint32_t Data1) 00107 { 00108 /* Update the DSI packet header with new information */ 00109 DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U)); 00110 } 00111 00112 /* Exported functions --------------------------------------------------------*/ 00113 /** @addtogroup DSI_Exported_Functions 00114 * @{ 00115 */ 00116 00117 /** @defgroup DSI_Group1 Initialization and Configuration functions 00118 * @brief Initialization and Configuration functions 00119 * 00120 @verbatim 00121 =============================================================================== 00122 ##### Initialization and Configuration functions ##### 00123 =============================================================================== 00124 [..] This section provides functions allowing to: 00125 (+) Initialize and configure the DSI 00126 (+) De-initialize the DSI 00127 00128 @endverbatim 00129 * @{ 00130 */ 00131 00132 /** 00133 * @brief Initializes the DSI according to the specified 00134 * parameters in the DSI_InitTypeDef and create the associated handle. 00135 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00136 * the configuration information for the DSI. 00137 * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains 00138 * the PLL Clock structure definition for the DSI. 00139 * @retval HAL status 00140 */ 00141 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) 00142 { 00143 uint32_t tickstart; 00144 uint32_t unitIntervalx4; 00145 uint32_t tempIDF; 00146 00147 /* Check the DSI handle allocation */ 00148 if(hdsi == NULL) 00149 { 00150 return HAL_ERROR; 00151 } 00152 00153 /* Check function parameters */ 00154 assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); 00155 assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); 00156 assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); 00157 assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); 00158 assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); 00159 00160 if(hdsi->State == HAL_DSI_STATE_RESET) 00161 { 00162 /* Initialize the low level hardware */ 00163 HAL_DSI_MspInit(hdsi); 00164 } 00165 00166 /* Change DSI peripheral state */ 00167 hdsi->State = HAL_DSI_STATE_BUSY; 00168 00169 /**************** Turn on the regulator and enable the DSI PLL ****************/ 00170 00171 /* Enable the regulator */ 00172 __HAL_DSI_REG_ENABLE(hdsi); 00173 00174 /* Get tick */ 00175 tickstart = HAL_GetTick(); 00176 00177 /* Wait until the regulator is ready */ 00178 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET) 00179 { 00180 /* Check for the Timeout */ 00181 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 00182 { 00183 return HAL_TIMEOUT; 00184 } 00185 } 00186 00187 /* Set the PLL division factors */ 00188 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); 00189 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U)); 00190 00191 /* Enable the DSI PLL */ 00192 __HAL_DSI_PLL_ENABLE(hdsi); 00193 00194 /* Get tick */ 00195 tickstart = HAL_GetTick(); 00196 00197 /* Wait for the lock of the PLL */ 00198 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) 00199 { 00200 /* Check for the Timeout */ 00201 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 00202 { 00203 return HAL_TIMEOUT; 00204 } 00205 } 00206 00207 /*************************** Set the PHY parameters ***************************/ 00208 00209 /* D-PHY clock and digital enable*/ 00210 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); 00211 00212 /* Clock lane configuration */ 00213 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); 00214 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); 00215 00216 /* Configure the number of active data lanes */ 00217 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; 00218 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; 00219 00220 /************************ Set the DSI clock parameters ************************/ 00221 00222 /* Set the TX escape clock division factor */ 00223 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; 00224 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; 00225 00226 /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ 00227 /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ 00228 /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ 00229 tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; 00230 unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); 00231 00232 /* Set the bit period in high-speed mode */ 00233 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; 00234 hdsi->Instance->WPCR[0U] |= unitIntervalx4; 00235 00236 /****************************** Error management *****************************/ 00237 00238 /* Disable all error interrupts and reset the Error Mask */ 00239 hdsi->Instance->IER[0U] = 0U; 00240 hdsi->Instance->IER[1U] = 0U; 00241 hdsi->ErrorMsk = 0U; 00242 00243 /* Initialise the error code */ 00244 hdsi->ErrorCode = HAL_DSI_ERROR_NONE; 00245 00246 /* Initialize the DSI state*/ 00247 hdsi->State = HAL_DSI_STATE_READY; 00248 00249 return HAL_OK; 00250 } 00251 00252 /** 00253 * @brief De-initializes the DSI peripheral registers to their default reset 00254 * values. 00255 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00256 * the configuration information for the DSI. 00257 * @retval HAL status 00258 */ 00259 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) 00260 { 00261 /* Check the DSI handle allocation */ 00262 if(hdsi == NULL) 00263 { 00264 return HAL_ERROR; 00265 } 00266 00267 /* Change DSI peripheral state */ 00268 hdsi->State = HAL_DSI_STATE_BUSY; 00269 00270 /* Disable the DSI wrapper */ 00271 __HAL_DSI_WRAPPER_DISABLE(hdsi); 00272 00273 /* Disable the DSI host */ 00274 __HAL_DSI_DISABLE(hdsi); 00275 00276 /* D-PHY clock and digital disable */ 00277 hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); 00278 00279 /* Turn off the DSI PLL */ 00280 __HAL_DSI_PLL_DISABLE(hdsi); 00281 00282 /* Disable the regulator */ 00283 __HAL_DSI_REG_DISABLE(hdsi); 00284 00285 /* DeInit the low level hardware */ 00286 HAL_DSI_MspDeInit(hdsi); 00287 00288 /* Initialise the error code */ 00289 hdsi->ErrorCode = HAL_DSI_ERROR_NONE; 00290 00291 /* Initialize the DSI state*/ 00292 hdsi->State = HAL_DSI_STATE_RESET; 00293 00294 /* Release Lock */ 00295 __HAL_UNLOCK(hdsi); 00296 00297 return HAL_OK; 00298 } 00299 00300 /** 00301 * @brief Enable the error monitor flags 00302 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00303 * the configuration information for the DSI. 00304 * @param ActiveErrors indicates which error interrupts will be enabled. 00305 * This parameter can be any combination of @ref DSI_Error_Data_Type. 00306 * @retval HAL status 00307 */ 00308 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) 00309 { 00310 /* Process locked */ 00311 __HAL_LOCK(hdsi); 00312 00313 hdsi->Instance->IER[0U] = 0U; 00314 hdsi->Instance->IER[1U] = 0U; 00315 00316 /* Store active errors to the handle */ 00317 hdsi->ErrorMsk = ActiveErrors; 00318 00319 if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET) 00320 { 00321 /* Enable the interrupt generation on selected errors */ 00322 hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; 00323 } 00324 00325 if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET) 00326 { 00327 /* Enable the interrupt generation on selected errors */ 00328 hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; 00329 } 00330 00331 if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET) 00332 { 00333 /* Enable the interrupt generation on selected errors */ 00334 hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; 00335 } 00336 00337 if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET) 00338 { 00339 /* Enable the interrupt generation on selected errors */ 00340 hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; 00341 } 00342 00343 if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET) 00344 { 00345 /* Enable the interrupt generation on selected errors */ 00346 hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; 00347 } 00348 00349 if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET) 00350 { 00351 /* Enable the interrupt generation on selected errors */ 00352 hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; 00353 } 00354 00355 if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET) 00356 { 00357 /* Enable the interrupt generation on selected errors */ 00358 hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; 00359 } 00360 00361 if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET) 00362 { 00363 /* Enable the interrupt generation on selected errors */ 00364 hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; 00365 } 00366 00367 if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET) 00368 { 00369 /* Enable the interrupt generation on selected errors */ 00370 hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; 00371 } 00372 00373 if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET) 00374 { 00375 /* Enable the interrupt generation on selected errors */ 00376 hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; 00377 } 00378 00379 /* Process Unlocked */ 00380 __HAL_UNLOCK(hdsi); 00381 00382 return HAL_OK; 00383 } 00384 00385 /** 00386 * @brief Initializes the DSI MSP. 00387 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00388 * the configuration information for the DSI. 00389 * @retval None 00390 */ 00391 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) 00392 { 00393 /* Prevent unused argument(s) compilation warning */ 00394 UNUSED(hdsi); 00395 /* NOTE : This function Should not be modified, when the callback is needed, 00396 the HAL_DSI_MspInit could be implemented in the user file 00397 */ 00398 } 00399 00400 /** 00401 * @brief De-initializes the DSI MSP. 00402 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00403 * the configuration information for the DSI. 00404 * @retval None 00405 */ 00406 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) 00407 { 00408 /* Prevent unused argument(s) compilation warning */ 00409 UNUSED(hdsi); 00410 /* NOTE : This function Should not be modified, when the callback is needed, 00411 the HAL_DSI_MspDeInit could be implemented in the user file 00412 */ 00413 } 00414 00415 /** 00416 * @} 00417 */ 00418 00419 /** @defgroup DSI_Group2 IO operation functions 00420 * @brief IO operation functions 00421 * 00422 @verbatim 00423 =============================================================================== 00424 ##### IO operation functions ##### 00425 =============================================================================== 00426 [..] This section provides function allowing to: 00427 (+) Handle DSI interrupt request 00428 00429 @endverbatim 00430 * @{ 00431 */ 00432 /** 00433 * @brief Handles DSI interrupt request. 00434 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00435 * the configuration information for the DSI. 00436 * @retval HAL status 00437 */ 00438 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) 00439 { 00440 uint32_t ErrorStatus0, ErrorStatus1; 00441 00442 /* Tearing Effect Interrupt management ***************************************/ 00443 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET) 00444 { 00445 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET) 00446 { 00447 /* Clear the Tearing Effect Interrupt Flag */ 00448 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); 00449 00450 /* Tearing Effect Callback */ 00451 HAL_DSI_TearingEffectCallback(hdsi); 00452 } 00453 } 00454 00455 /* End of Refresh Interrupt management ***************************************/ 00456 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET) 00457 { 00458 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET) 00459 { 00460 /* Clear the End of Refresh Interrupt Flag */ 00461 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); 00462 00463 /* End of Refresh Callback */ 00464 HAL_DSI_EndOfRefreshCallback(hdsi); 00465 } 00466 } 00467 00468 /* Error Interrupts management ***********************************************/ 00469 if(hdsi->ErrorMsk != 0U) 00470 { 00471 ErrorStatus0 = hdsi->Instance->ISR[0U]; 00472 ErrorStatus0 &= hdsi->Instance->IER[0U]; 00473 ErrorStatus1 = hdsi->Instance->ISR[1U]; 00474 ErrorStatus1 &= hdsi->Instance->IER[1U]; 00475 00476 if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET) 00477 { 00478 hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; 00479 } 00480 00481 if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET) 00482 { 00483 hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; 00484 } 00485 00486 if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET) 00487 { 00488 hdsi->ErrorCode |= HAL_DSI_ERROR_TX; 00489 } 00490 00491 if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET) 00492 { 00493 hdsi->ErrorCode |= HAL_DSI_ERROR_RX; 00494 } 00495 00496 if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET) 00497 { 00498 hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; 00499 } 00500 00501 if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET) 00502 { 00503 hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; 00504 } 00505 00506 if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET) 00507 { 00508 hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; 00509 } 00510 00511 if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET) 00512 { 00513 hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; 00514 } 00515 00516 if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET) 00517 { 00518 hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; 00519 } 00520 00521 if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET) 00522 { 00523 hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; 00524 } 00525 00526 /* Check only selected errors */ 00527 if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) 00528 { 00529 /* DSI error interrupt user callback */ 00530 HAL_DSI_ErrorCallback(hdsi); 00531 } 00532 } 00533 } 00534 00535 /** 00536 * @brief Tearing Effect DSI callback. 00537 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00538 * the configuration information for the DSI. 00539 * @retval None 00540 */ 00541 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) 00542 { 00543 /* Prevent unused argument(s) compilation warning */ 00544 UNUSED(hdsi); 00545 /* NOTE : This function Should not be modified, when the callback is needed, 00546 the HAL_DSI_TearingEffectCallback could be implemented in the user file 00547 */ 00548 } 00549 00550 /** 00551 * @brief End of Refresh DSI callback. 00552 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00553 * the configuration information for the DSI. 00554 * @retval None 00555 */ 00556 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) 00557 { 00558 /* Prevent unused argument(s) compilation warning */ 00559 UNUSED(hdsi); 00560 /* NOTE : This function Should not be modified, when the callback is needed, 00561 the HAL_DSI_EndOfRefreshCallback could be implemented in the user file 00562 */ 00563 } 00564 00565 /** 00566 * @brief Operation Error DSI callback. 00567 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00568 * the configuration information for the DSI. 00569 * @retval None 00570 */ 00571 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) 00572 { 00573 /* Prevent unused argument(s) compilation warning */ 00574 UNUSED(hdsi); 00575 /* NOTE : This function Should not be modified, when the callback is needed, 00576 the HAL_DSI_ErrorCallback could be implemented in the user file 00577 */ 00578 } 00579 00580 /** 00581 * @} 00582 */ 00583 00584 /** @defgroup DSI_Group3 Peripheral Control functions 00585 * @brief Peripheral Control functions 00586 * 00587 @verbatim 00588 =============================================================================== 00589 ##### Peripheral Control functions ##### 00590 =============================================================================== 00591 [..] This section provides functions allowing to: 00592 (+) Configure the Generic interface read-back Virtual Channel ID 00593 (+) Select video mode and configure the corresponding parameters 00594 (+) Configure command transmission mode: High-speed or Low-power 00595 (+) Configure the flow control 00596 (+) Configure the DSI PHY timer 00597 (+) Configure the DSI HOST timeout 00598 (+) Configure the DSI HOST timeout 00599 (+) Start/Stop the DSI module 00600 (+) Refresh the display in command mode 00601 (+) Controls the display color mode in Video mode 00602 (+) Control the display shutdown in Video mode 00603 (+) write short DCS or short Generic command 00604 (+) write long DCS or long Generic command 00605 (+) Read command (DCS or generic) 00606 (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running) 00607 (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off) 00608 (+) Start/Stop test pattern generation 00609 (+) Slew-Rate And Delay Tuning 00610 (+) Low-Power Reception Filter Tuning 00611 (+) Activate an additional current path on all lanes to meet the SDDTx parameter 00612 (+) Custom lane pins configuration 00613 (+) Set custom timing for the PHY 00614 (+) Force the Clock/Data Lane in TX Stop Mode 00615 (+) Force LP Receiver in Low-Power Mode 00616 (+) Force Data Lanes in RX Mode after a BTA 00617 (+) Enable a pull-down on the lanes to prevent from floating states when unused 00618 (+) Switch off the contention detection on data lanes 00619 00620 @endverbatim 00621 * @{ 00622 */ 00623 00624 /** 00625 * @brief Configure the Generic interface read-back Virtual Channel ID. 00626 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00627 * the configuration information for the DSI. 00628 * @param VirtualChannelID Virtual channel ID 00629 * @retval HAL status 00630 */ 00631 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) 00632 { 00633 /* Process locked */ 00634 __HAL_LOCK(hdsi); 00635 00636 /* Update the GVCID register */ 00637 hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; 00638 hdsi->Instance->GVCIDR |= VirtualChannelID; 00639 00640 /* Process unlocked */ 00641 __HAL_UNLOCK(hdsi); 00642 00643 return HAL_OK; 00644 } 00645 00646 /** 00647 * @brief Select video mode and configure the corresponding parameters 00648 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00649 * the configuration information for the DSI. 00650 * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains 00651 * the DSI video mode configuration parameters 00652 * @retval HAL status 00653 */ 00654 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) 00655 { 00656 /* Process locked */ 00657 __HAL_LOCK(hdsi); 00658 00659 /* Check the parameters */ 00660 assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); 00661 assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); 00662 assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); 00663 assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); 00664 assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); 00665 assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); 00666 assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); 00667 assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); 00668 assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); 00669 assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); 00670 assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); 00671 assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); 00672 assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); 00673 /* Check the LooselyPacked variant only in 18-bit mode */ 00674 if(VidCfg->ColorCoding == DSI_RGB666) 00675 { 00676 assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); 00677 } 00678 00679 /* Select video mode by resetting CMDM and DSIM bits */ 00680 hdsi->Instance->MCR &= ~DSI_MCR_CMDM; 00681 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; 00682 00683 /* Configure the video mode transmission type */ 00684 hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; 00685 hdsi->Instance->VMCR |= VidCfg->Mode; 00686 00687 /* Configure the video packet size */ 00688 hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; 00689 hdsi->Instance->VPCR |= VidCfg->PacketSize; 00690 00691 /* Set the chunks number to be transmitted through the DSI link */ 00692 hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; 00693 hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; 00694 00695 /* Set the size of the null packet */ 00696 hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; 00697 hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; 00698 00699 /* Select the virtual channel for the LTDC interface traffic */ 00700 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; 00701 hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; 00702 00703 /* Configure the polarity of control signals */ 00704 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); 00705 hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); 00706 00707 /* Select the color coding for the host */ 00708 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; 00709 hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; 00710 00711 /* Select the color coding for the wrapper */ 00712 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; 00713 hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U); 00714 00715 /* Enable/disable the loosely packed variant to 18-bit configuration */ 00716 if(VidCfg->ColorCoding == DSI_RGB666) 00717 { 00718 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; 00719 hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; 00720 } 00721 00722 /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ 00723 hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; 00724 hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; 00725 00726 /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ 00727 hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; 00728 hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; 00729 00730 /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ 00731 hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; 00732 hdsi->Instance->VLCR |= VidCfg->HorizontalLine; 00733 00734 /* Set the Vertical Synchronization Active (VSA) */ 00735 hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; 00736 hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; 00737 00738 /* Set the Vertical Back Porch (VBP)*/ 00739 hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; 00740 hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; 00741 00742 /* Set the Vertical Front Porch (VFP)*/ 00743 hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; 00744 hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; 00745 00746 /* Set the Vertical Active period*/ 00747 hdsi->Instance->VVACR &= ~DSI_VVACR_VA; 00748 hdsi->Instance->VVACR |= VidCfg->VerticalActive; 00749 00750 /* Configure the command transmission mode */ 00751 hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; 00752 hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; 00753 00754 /* Low power largest packet size */ 00755 hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; 00756 hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U); 00757 00758 /* Low power VACT largest packet size */ 00759 hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; 00760 hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; 00761 00762 /* Enable LP transition in HFP period */ 00763 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; 00764 hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; 00765 00766 /* Enable LP transition in HBP period */ 00767 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; 00768 hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; 00769 00770 /* Enable LP transition in VACT period */ 00771 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; 00772 hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; 00773 00774 /* Enable LP transition in VFP period */ 00775 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; 00776 hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; 00777 00778 /* Enable LP transition in VBP period */ 00779 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; 00780 hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; 00781 00782 /* Enable LP transition in vertical sync period */ 00783 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; 00784 hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; 00785 00786 /* Enable the request for an acknowledge response at the end of a frame */ 00787 hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; 00788 hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; 00789 00790 /* Process unlocked */ 00791 __HAL_UNLOCK(hdsi); 00792 00793 return HAL_OK; 00794 } 00795 00796 /** 00797 * @brief Select adapted command mode and configure the corresponding parameters 00798 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00799 * the configuration information for the DSI. 00800 * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains 00801 * the DSI command mode configuration parameters 00802 * @retval HAL status 00803 */ 00804 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) 00805 { 00806 /* Process locked */ 00807 __HAL_LOCK(hdsi); 00808 00809 /* Check the parameters */ 00810 assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); 00811 assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); 00812 assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); 00813 assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); 00814 assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); 00815 assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); 00816 assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); 00817 assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); 00818 assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); 00819 00820 /* Select command mode by setting CMDM and DSIM bits */ 00821 hdsi->Instance->MCR |= DSI_MCR_CMDM; 00822 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; 00823 hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; 00824 00825 /* Select the virtual channel for the LTDC interface traffic */ 00826 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; 00827 hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; 00828 00829 /* Configure the polarity of control signals */ 00830 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); 00831 hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); 00832 00833 /* Select the color coding for the host */ 00834 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; 00835 hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; 00836 00837 /* Select the color coding for the wrapper */ 00838 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; 00839 hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U); 00840 00841 /* Configure the maximum allowed size for write memory command */ 00842 hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; 00843 hdsi->Instance->LCCR |= CmdCfg->CommandSize; 00844 00845 /* Configure the tearing effect source and polarity and select the refresh mode */ 00846 hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); 00847 hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); 00848 00849 /* Configure the tearing effect acknowledge request */ 00850 hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; 00851 hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; 00852 00853 /* Enable the Tearing Effect interrupt */ 00854 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); 00855 00856 /* Enable the End of Refresh interrupt */ 00857 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); 00858 00859 /* Process unlocked */ 00860 __HAL_UNLOCK(hdsi); 00861 00862 return HAL_OK; 00863 } 00864 00865 /** 00866 * @brief Configure command transmission mode: High-speed or Low-power 00867 * and enable/disable acknowledge request after packet transmission 00868 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00869 * the configuration information for the DSI. 00870 * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains 00871 * the DSI command transmission mode configuration parameters 00872 * @retval HAL status 00873 */ 00874 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) 00875 { 00876 /* Process locked */ 00877 __HAL_LOCK(hdsi); 00878 00879 assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); 00880 assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); 00881 assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); 00882 assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); 00883 assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); 00884 assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); 00885 assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); 00886 assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); 00887 assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); 00888 assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); 00889 assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); 00890 assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); 00891 assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); 00892 00893 /* Select High-speed or Low-power for command transmission */ 00894 hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ 00895 DSI_CMCR_GSW1TX |\ 00896 DSI_CMCR_GSW2TX |\ 00897 DSI_CMCR_GSR0TX |\ 00898 DSI_CMCR_GSR1TX |\ 00899 DSI_CMCR_GSR2TX |\ 00900 DSI_CMCR_GLWTX |\ 00901 DSI_CMCR_DSW0TX |\ 00902 DSI_CMCR_DSW1TX |\ 00903 DSI_CMCR_DSR0TX |\ 00904 DSI_CMCR_DLWTX |\ 00905 DSI_CMCR_MRDPS); 00906 hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\ 00907 LPCmd->LPGenShortWriteOneP |\ 00908 LPCmd->LPGenShortWriteTwoP |\ 00909 LPCmd->LPGenShortReadNoP |\ 00910 LPCmd->LPGenShortReadOneP |\ 00911 LPCmd->LPGenShortReadTwoP |\ 00912 LPCmd->LPGenLongWrite |\ 00913 LPCmd->LPDcsShortWriteNoP |\ 00914 LPCmd->LPDcsShortWriteOneP |\ 00915 LPCmd->LPDcsShortReadNoP |\ 00916 LPCmd->LPDcsLongWrite |\ 00917 LPCmd->LPMaxReadPacket); 00918 00919 /* Configure the acknowledge request after each packet transmission */ 00920 hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; 00921 hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; 00922 00923 /* Process unlocked */ 00924 __HAL_UNLOCK(hdsi); 00925 00926 return HAL_OK; 00927 } 00928 00929 /** 00930 * @brief Configure the flow control parameters 00931 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00932 * the configuration information for the DSI. 00933 * @param FlowControl flow control feature(s) to be enabled. 00934 * This parameter can be any combination of @ref DSI_FlowControl. 00935 * @retval HAL status 00936 */ 00937 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) 00938 { 00939 /* Process locked */ 00940 __HAL_LOCK(hdsi); 00941 00942 /* Check the parameters */ 00943 assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); 00944 00945 /* Set the DSI Host Protocol Configuration Register */ 00946 hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; 00947 hdsi->Instance->PCR |= FlowControl; 00948 00949 /* Process unlocked */ 00950 __HAL_UNLOCK(hdsi); 00951 00952 return HAL_OK; 00953 } 00954 00955 /** 00956 * @brief Configure the DSI PHY timer parameters 00957 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00958 * the configuration information for the DSI. 00959 * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains 00960 * the DSI PHY timing parameters 00961 * @retval HAL status 00962 */ 00963 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) 00964 { 00965 uint32_t maxTime; 00966 /* Process locked */ 00967 __HAL_LOCK(hdsi); 00968 00969 maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; 00970 00971 /* Clock lane timer configuration */ 00972 00973 /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two 00974 High-Speed transmission. 00975 To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed 00976 to Low-Power and from Low-Power to High-Speed. 00977 This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). 00978 But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. 00979 00980 Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. 00981 */ 00982 hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); 00983 hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U)); 00984 00985 /* Data lane timer configuration */ 00986 hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); 00987 hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U)); 00988 00989 /* Configure the wait period to request HS transmission after a stop state */ 00990 hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; 00991 hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U); 00992 00993 /* Process unlocked */ 00994 __HAL_UNLOCK(hdsi); 00995 00996 return HAL_OK; 00997 } 00998 00999 /** 01000 * @brief Configure the DSI HOST timeout parameters 01001 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01002 * the configuration information for the DSI. 01003 * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains 01004 * the DSI host timeout parameters 01005 * @retval HAL status 01006 */ 01007 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) 01008 { 01009 /* Process locked */ 01010 __HAL_LOCK(hdsi); 01011 01012 /* Set the timeout clock division factor */ 01013 hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; 01014 hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U); 01015 01016 /* High-speed transmission timeout */ 01017 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; 01018 hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U); 01019 01020 /* Low-power reception timeout */ 01021 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; 01022 hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout; 01023 01024 /* High-speed read timeout */ 01025 hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT; 01026 hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout; 01027 01028 /* Low-power read timeout */ 01029 hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT; 01030 hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout; 01031 01032 /* High-speed write timeout */ 01033 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT; 01034 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout; 01035 01036 /* High-speed write presp mode */ 01037 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM; 01038 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode; 01039 01040 /* Low-speed write timeout */ 01041 hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT; 01042 hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout; 01043 01044 /* BTA timeout */ 01045 hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT; 01046 hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout; 01047 01048 /* Process unlocked */ 01049 __HAL_UNLOCK(hdsi); 01050 01051 return HAL_OK; 01052 } 01053 01054 /** 01055 * @brief Start the DSI module 01056 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01057 * the configuration information for the DSI. 01058 * @retval HAL status 01059 */ 01060 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) 01061 { 01062 /* Process locked */ 01063 __HAL_LOCK(hdsi); 01064 01065 /* Enable the DSI host */ 01066 __HAL_DSI_ENABLE(hdsi); 01067 01068 /* Enable the DSI wrapper */ 01069 __HAL_DSI_WRAPPER_ENABLE(hdsi); 01070 01071 /* Process unlocked */ 01072 __HAL_UNLOCK(hdsi); 01073 01074 return HAL_OK; 01075 } 01076 01077 /** 01078 * @brief Stop the DSI module 01079 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01080 * the configuration information for the DSI. 01081 * @retval HAL status 01082 */ 01083 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) 01084 { 01085 /* Process locked */ 01086 __HAL_LOCK(hdsi); 01087 01088 /* Disable the DSI host */ 01089 __HAL_DSI_DISABLE(hdsi); 01090 01091 /* Disable the DSI wrapper */ 01092 __HAL_DSI_WRAPPER_DISABLE(hdsi); 01093 01094 /* Process unlocked */ 01095 __HAL_UNLOCK(hdsi); 01096 01097 return HAL_OK; 01098 } 01099 01100 /** 01101 * @brief Refresh the display in command mode 01102 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01103 * the configuration information for the DSI. 01104 * @retval HAL status 01105 */ 01106 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) 01107 { 01108 /* Process locked */ 01109 __HAL_LOCK(hdsi); 01110 01111 /* Update the display */ 01112 hdsi->Instance->WCR |= DSI_WCR_LTDCEN; 01113 01114 /* Process unlocked */ 01115 __HAL_UNLOCK(hdsi); 01116 01117 return HAL_OK; 01118 } 01119 01120 /** 01121 * @brief Controls the display color mode in Video mode 01122 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01123 * the configuration information for the DSI. 01124 * @param ColorMode Color mode (full or 8-colors). 01125 * This parameter can be any value of @ref DSI_Color_Mode 01126 * @retval HAL status 01127 */ 01128 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) 01129 { 01130 /* Process locked */ 01131 __HAL_LOCK(hdsi); 01132 01133 /* Check the parameters */ 01134 assert_param(IS_DSI_COLOR_MODE(ColorMode)); 01135 01136 /* Update the display color mode */ 01137 hdsi->Instance->WCR &= ~DSI_WCR_COLM; 01138 hdsi->Instance->WCR |= ColorMode; 01139 01140 /* Process unlocked */ 01141 __HAL_UNLOCK(hdsi); 01142 01143 return HAL_OK; 01144 } 01145 01146 /** 01147 * @brief Control the display shutdown in Video mode 01148 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01149 * the configuration information for the DSI. 01150 * @param Shutdown Shut-down (Display-ON or Display-OFF). 01151 * This parameter can be any value of @ref DSI_ShutDown 01152 * @retval HAL status 01153 */ 01154 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) 01155 { 01156 /* Process locked */ 01157 __HAL_LOCK(hdsi); 01158 01159 /* Check the parameters */ 01160 assert_param(IS_DSI_SHUT_DOWN(Shutdown)); 01161 01162 /* Update the display Shutdown */ 01163 hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; 01164 hdsi->Instance->WCR |= Shutdown; 01165 01166 /* Process unlocked */ 01167 __HAL_UNLOCK(hdsi); 01168 01169 return HAL_OK; 01170 } 01171 01172 /** 01173 * @brief write short DCS or short Generic command 01174 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01175 * the configuration information for the DSI. 01176 * @param ChannelID Virtual channel ID. 01177 * @param Mode DSI short packet data type. 01178 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. 01179 * @param Param1 DSC command or first generic parameter. 01180 * This parameter can be any value of @ref DSI_DCS_Command or a 01181 * generic command code. 01182 * @param Param2 DSC parameter or second generic parameter. 01183 * @retval HAL status 01184 */ 01185 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 01186 uint32_t ChannelID, 01187 uint32_t Mode, 01188 uint32_t Param1, 01189 uint32_t Param2) 01190 { 01191 uint32_t tickstart; 01192 01193 /* Process locked */ 01194 __HAL_LOCK(hdsi); 01195 01196 /* Check the parameters */ 01197 assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); 01198 01199 /* Get tick */ 01200 tickstart = HAL_GetTick(); 01201 01202 /* Wait for Command FIFO Empty */ 01203 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) 01204 { 01205 /* Check for the Timeout */ 01206 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01207 { 01208 /* Process Unlocked */ 01209 __HAL_UNLOCK(hdsi); 01210 01211 return HAL_TIMEOUT; 01212 } 01213 } 01214 01215 /* Configure the packet to send a short DCS command with 0 or 1 parameter */ 01216 DSI_ConfigPacketHeader(hdsi->Instance, 01217 ChannelID, 01218 Mode, 01219 Param1, 01220 Param2); 01221 01222 /* Process unlocked */ 01223 __HAL_UNLOCK(hdsi); 01224 01225 return HAL_OK; 01226 } 01227 01228 /** 01229 * @brief write long DCS or long Generic command 01230 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01231 * the configuration information for the DSI. 01232 * @param ChannelID Virtual channel ID. 01233 * @param Mode DSI long packet data type. 01234 * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. 01235 * @param NbParams Number of parameters. 01236 * @param Param1 DSC command or first generic parameter. 01237 * This parameter can be any value of @ref DSI_DCS_Command or a 01238 * generic command code 01239 * @param ParametersTable Pointer to parameter values table. 01240 * @retval HAL status 01241 */ 01242 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 01243 uint32_t ChannelID, 01244 uint32_t Mode, 01245 uint32_t NbParams, 01246 uint32_t Param1, 01247 uint8_t* ParametersTable) 01248 { 01249 uint32_t uicounter, nbBytes, count; 01250 uint32_t tickstart; 01251 uint32_t fifoword; 01252 uint8_t* pparams = ParametersTable; 01253 01254 /* Process locked */ 01255 __HAL_LOCK(hdsi); 01256 01257 /* Check the parameters */ 01258 assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); 01259 01260 /* Get tick */ 01261 tickstart = HAL_GetTick(); 01262 01263 /* Wait for Command FIFO Empty */ 01264 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET) 01265 { 01266 /* Check for the Timeout */ 01267 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01268 { 01269 /* Process Unlocked */ 01270 __HAL_UNLOCK(hdsi); 01271 01272 return HAL_TIMEOUT; 01273 } 01274 } 01275 01276 /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/ 01277 fifoword = Param1; 01278 nbBytes = (NbParams < 3U) ? NbParams : 3U; 01279 01280 for(count = 0U; count < nbBytes; count++) 01281 { 01282 fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count))); 01283 } 01284 hdsi->Instance->GPDR = fifoword; 01285 01286 uicounter = NbParams - nbBytes; 01287 pparams += nbBytes; 01288 /* Set the Next parameters on the write FIFO command*/ 01289 while(uicounter != 0U) 01290 { 01291 nbBytes = (uicounter < 4U) ? uicounter : 4U; 01292 fifoword = 0U; 01293 for(count = 0U; count < nbBytes; count++) 01294 { 01295 fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count)); 01296 } 01297 hdsi->Instance->GPDR = fifoword; 01298 01299 uicounter -= nbBytes; 01300 pparams += nbBytes; 01301 } 01302 01303 /* Configure the packet to send a long DCS command */ 01304 DSI_ConfigPacketHeader(hdsi->Instance, 01305 ChannelID, 01306 Mode, 01307 ((NbParams+1U)&0x00FFU), 01308 (((NbParams+1U)&0xFF00U)>>8U)); 01309 01310 /* Process unlocked */ 01311 __HAL_UNLOCK(hdsi); 01312 01313 return HAL_OK; 01314 } 01315 01316 /** 01317 * @brief Read command (DCS or generic) 01318 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01319 * the configuration information for the DSI. 01320 * @param ChannelNbr Virtual channel ID 01321 * @param Array pointer to a buffer to store the payload of a read back operation. 01322 * @param Size Data size to be read (in byte). 01323 * @param Mode DSI read packet data type. 01324 * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. 01325 * @param DCSCmd DCS get/read command. 01326 * @param ParametersTable Pointer to parameter values table. 01327 * @retval HAL status 01328 */ 01329 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 01330 uint32_t ChannelNbr, 01331 uint8_t* Array, 01332 uint32_t Size, 01333 uint32_t Mode, 01334 uint32_t DCSCmd, 01335 uint8_t* ParametersTable) 01336 { 01337 uint32_t tickstart; 01338 uint8_t* pdata = Array; 01339 uint32_t datasize = Size; 01340 01341 /* Process locked */ 01342 __HAL_LOCK(hdsi); 01343 01344 /* Check the parameters */ 01345 assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); 01346 01347 if(datasize > 2U) 01348 { 01349 /* set max return packet size */ 01350 if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK) 01351 { 01352 /* Process Unlocked */ 01353 __HAL_UNLOCK(hdsi); 01354 01355 return HAL_ERROR; 01356 } 01357 } 01358 01359 /* Configure the packet to read command */ 01360 if (Mode == DSI_DCS_SHORT_PKT_READ) 01361 { 01362 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U); 01363 } 01364 else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) 01365 { 01366 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U); 01367 } 01368 else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) 01369 { 01370 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U); 01371 } 01372 else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) 01373 { 01374 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]); 01375 } 01376 else 01377 { 01378 /* Process Unlocked */ 01379 __HAL_UNLOCK(hdsi); 01380 01381 return HAL_ERROR; 01382 } 01383 01384 /* Get tick */ 01385 tickstart = HAL_GetTick(); 01386 01387 /* Check that the payload read FIFO is not empty */ 01388 while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE) 01389 { 01390 /* Check for the Timeout */ 01391 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01392 { 01393 /* Process Unlocked */ 01394 __HAL_UNLOCK(hdsi); 01395 01396 return HAL_TIMEOUT; 01397 } 01398 } 01399 01400 /* Get the first byte */ 01401 *((uint32_t *)pdata) = (hdsi->Instance->GPDR); 01402 if (datasize > 4U) 01403 { 01404 datasize -= 4U; 01405 pdata += 4U; 01406 } 01407 else 01408 { 01409 /* Process unlocked */ 01410 __HAL_UNLOCK(hdsi); 01411 01412 return HAL_OK; 01413 } 01414 01415 /* Get tick */ 01416 tickstart = HAL_GetTick(); 01417 01418 /* Get the remaining bytes if any */ 01419 while(((int)(datasize)) > 0) 01420 { 01421 if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) 01422 { 01423 *((uint32_t *)pdata) = (hdsi->Instance->GPDR); 01424 datasize -= 4U; 01425 pdata += 4U; 01426 } 01427 01428 /* Check for the Timeout */ 01429 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01430 { 01431 /* Process Unlocked */ 01432 __HAL_UNLOCK(hdsi); 01433 01434 return HAL_TIMEOUT; 01435 } 01436 } 01437 01438 /* Process unlocked */ 01439 __HAL_UNLOCK(hdsi); 01440 01441 return HAL_OK; 01442 } 01443 01444 /** 01445 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running 01446 * (only data lanes are in ULPM) 01447 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01448 * the configuration information for the DSI. 01449 * @retval HAL status 01450 */ 01451 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) 01452 { 01453 uint32_t tickstart; 01454 01455 /* Process locked */ 01456 __HAL_LOCK(hdsi); 01457 01458 /* ULPS Request on Data Lanes */ 01459 hdsi->Instance->PUCR |= DSI_PUCR_URDL; 01460 01461 /* Get tick */ 01462 tickstart = HAL_GetTick(); 01463 01464 /* Wait until the D-PHY active lanes enter into ULPM */ 01465 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) 01466 { 01467 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET) 01468 { 01469 /* Check for the Timeout */ 01470 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01471 { 01472 /* Process Unlocked */ 01473 __HAL_UNLOCK(hdsi); 01474 01475 return HAL_TIMEOUT; 01476 } 01477 } 01478 } 01479 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) 01480 { 01481 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET) 01482 { 01483 /* Check for the Timeout */ 01484 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01485 { 01486 /* Process Unlocked */ 01487 __HAL_UNLOCK(hdsi); 01488 01489 return HAL_TIMEOUT; 01490 } 01491 } 01492 } 01493 else 01494 { 01495 /* Process unlocked */ 01496 __HAL_UNLOCK(hdsi); 01497 01498 return HAL_ERROR; 01499 } 01500 01501 /* Process unlocked */ 01502 __HAL_UNLOCK(hdsi); 01503 01504 return HAL_OK; 01505 } 01506 01507 /** 01508 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running 01509 * (only data lanes are in ULPM) 01510 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01511 * the configuration information for the DSI. 01512 * @retval HAL status 01513 */ 01514 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) 01515 { 01516 uint32_t tickstart; 01517 01518 /* Process locked */ 01519 __HAL_LOCK(hdsi); 01520 01521 /* Exit ULPS on Data Lanes */ 01522 hdsi->Instance->PUCR |= DSI_PUCR_UEDL; 01523 01524 /* Get tick */ 01525 tickstart = HAL_GetTick(); 01526 01527 /* Wait until all active lanes exit ULPM */ 01528 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) 01529 { 01530 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) 01531 { 01532 /* Check for the Timeout */ 01533 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01534 { 01535 /* Process Unlocked */ 01536 __HAL_UNLOCK(hdsi); 01537 01538 return HAL_TIMEOUT; 01539 } 01540 } 01541 } 01542 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) 01543 { 01544 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) 01545 { 01546 /* Check for the Timeout */ 01547 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01548 { 01549 /* Process Unlocked */ 01550 __HAL_UNLOCK(hdsi); 01551 01552 return HAL_TIMEOUT; 01553 } 01554 } 01555 } 01556 else 01557 { 01558 /* Process unlocked */ 01559 __HAL_UNLOCK(hdsi); 01560 01561 return HAL_ERROR; 01562 } 01563 01564 /* wait for 1 ms*/ 01565 HAL_Delay(1U); 01566 01567 /* De-assert the ULPM requests and the ULPM exit bits */ 01568 hdsi->Instance->PUCR = 0U; 01569 01570 /* Process unlocked */ 01571 __HAL_UNLOCK(hdsi); 01572 01573 return HAL_OK; 01574 } 01575 01576 /** 01577 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off 01578 * (both data and clock lanes are in ULPM) 01579 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01580 * the configuration information for the DSI. 01581 * @retval HAL status 01582 */ 01583 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) 01584 { 01585 uint32_t tickstart; 01586 01587 /* Process locked */ 01588 __HAL_LOCK(hdsi); 01589 01590 /* Clock lane configuration: no more HS request */ 01591 hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; 01592 01593 /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ 01594 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR); 01595 01596 /* ULPS Request on Clock and Data Lanes */ 01597 hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); 01598 01599 /* Get tick */ 01600 tickstart = HAL_GetTick(); 01601 01602 /* Wait until all active lanes exit ULPM */ 01603 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) 01604 { 01605 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET) 01606 { 01607 /* Check for the Timeout */ 01608 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01609 { 01610 /* Process Unlocked */ 01611 __HAL_UNLOCK(hdsi); 01612 01613 return HAL_TIMEOUT; 01614 } 01615 } 01616 } 01617 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) 01618 { 01619 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET) 01620 { 01621 /* Check for the Timeout */ 01622 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01623 { 01624 /* Process Unlocked */ 01625 __HAL_UNLOCK(hdsi); 01626 01627 return HAL_TIMEOUT; 01628 } 01629 } 01630 } 01631 else 01632 { 01633 /* Process unlocked */ 01634 __HAL_UNLOCK(hdsi); 01635 01636 return HAL_ERROR; 01637 } 01638 01639 /* Turn off the DSI PLL */ 01640 __HAL_DSI_PLL_DISABLE(hdsi); 01641 01642 /* Process unlocked */ 01643 __HAL_UNLOCK(hdsi); 01644 01645 return HAL_OK; 01646 } 01647 01648 /** 01649 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off 01650 * (both data and clock lanes are in ULPM) 01651 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01652 * the configuration information for the DSI. 01653 * @retval HAL status 01654 */ 01655 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) 01656 { 01657 uint32_t tickstart; 01658 01659 /* Process locked */ 01660 __HAL_LOCK(hdsi); 01661 01662 /* Turn on the DSI PLL */ 01663 __HAL_DSI_PLL_ENABLE(hdsi); 01664 01665 /* Get tick */ 01666 tickstart = HAL_GetTick(); 01667 01668 /* Wait for the lock of the PLL */ 01669 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET) 01670 { 01671 /* Check for the Timeout */ 01672 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01673 { 01674 /* Process Unlocked */ 01675 __HAL_UNLOCK(hdsi); 01676 01677 return HAL_TIMEOUT; 01678 } 01679 } 01680 01681 /* Exit ULPS on Clock and Data Lanes */ 01682 hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); 01683 01684 /* Get tick */ 01685 tickstart = HAL_GetTick(); 01686 01687 /* Wait until all active lanes exit ULPM */ 01688 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) 01689 { 01690 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) 01691 { 01692 /* Check for the Timeout */ 01693 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01694 { 01695 /* Process Unlocked */ 01696 __HAL_UNLOCK(hdsi); 01697 01698 return HAL_TIMEOUT; 01699 } 01700 } 01701 } 01702 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) 01703 { 01704 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) 01705 { 01706 /* Check for the Timeout */ 01707 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01708 { 01709 /* Process Unlocked */ 01710 __HAL_UNLOCK(hdsi); 01711 01712 return HAL_TIMEOUT; 01713 } 01714 } 01715 } 01716 else 01717 { 01718 /* Process unlocked */ 01719 __HAL_UNLOCK(hdsi); 01720 01721 return HAL_ERROR; 01722 } 01723 01724 /* wait for 1 ms */ 01725 HAL_Delay(1U); 01726 01727 /* De-assert the ULPM requests and the ULPM exit bits */ 01728 hdsi->Instance->PUCR = 0U; 01729 01730 /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ 01731 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); 01732 01733 /* Restore clock lane configuration to HS */ 01734 hdsi->Instance->CLCR |= DSI_CLCR_DPCC; 01735 01736 /* Process unlocked */ 01737 __HAL_UNLOCK(hdsi); 01738 01739 return HAL_OK; 01740 } 01741 01742 /** 01743 * @brief Start test pattern generation 01744 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01745 * the configuration information for the DSI. 01746 * @param Mode Pattern generator mode 01747 * This parameter can be one of the following values: 01748 * 0 : Color bars (horizontal or vertical) 01749 * 1 : BER pattern (vertical only) 01750 * @param Orientation Pattern generator orientation 01751 * This parameter can be one of the following values: 01752 * 0 : Vertical color bars 01753 * 1 : Horizontal color bars 01754 * @retval HAL status 01755 */ 01756 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) 01757 { 01758 /* Process locked */ 01759 __HAL_LOCK(hdsi); 01760 01761 /* Configure pattern generator mode and orientation */ 01762 hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); 01763 hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U)); 01764 01765 /* Enable pattern generator by setting PGE bit */ 01766 hdsi->Instance->VMCR |= DSI_VMCR_PGE; 01767 01768 /* Process unlocked */ 01769 __HAL_UNLOCK(hdsi); 01770 01771 return HAL_OK; 01772 } 01773 01774 /** 01775 * @brief Stop test pattern generation 01776 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01777 * the configuration information for the DSI. 01778 * @retval HAL status 01779 */ 01780 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) 01781 { 01782 /* Process locked */ 01783 __HAL_LOCK(hdsi); 01784 01785 /* Disable pattern generator by clearing PGE bit */ 01786 hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; 01787 01788 /* Process unlocked */ 01789 __HAL_UNLOCK(hdsi); 01790 01791 return HAL_OK; 01792 } 01793 01794 /** 01795 * @brief Set Slew-Rate And Delay Tuning 01796 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01797 * the configuration information for the DSI. 01798 * @param CommDelay Communication delay to be adjusted. 01799 * This parameter can be any value of @ref DSI_Communication_Delay 01800 * @param Lane select between clock or data lanes. 01801 * This parameter can be any value of @ref DSI_Lane_Group 01802 * @param Value Custom value of the slew-rate or delay 01803 * @retval HAL status 01804 */ 01805 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) 01806 { 01807 /* Process locked */ 01808 __HAL_LOCK(hdsi); 01809 01810 /* Check function parameters */ 01811 assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); 01812 assert_param(IS_DSI_LANE_GROUP(Lane)); 01813 01814 switch(CommDelay) 01815 { 01816 case DSI_SLEW_RATE_HSTX: 01817 if(Lane == DSI_CLOCK_LANE) 01818 { 01819 /* High-Speed Transmission Slew Rate Control on Clock Lane */ 01820 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL; 01821 hdsi->Instance->WPCR[1U] |= Value<<16U; 01822 } 01823 else if(Lane == DSI_DATA_LANES) 01824 { 01825 /* High-Speed Transmission Slew Rate Control on Data Lanes */ 01826 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; 01827 hdsi->Instance->WPCR[1U] |= Value<<18U; 01828 } 01829 else 01830 { 01831 /* Process unlocked */ 01832 __HAL_UNLOCK(hdsi); 01833 01834 return HAL_ERROR; 01835 } 01836 break; 01837 case DSI_SLEW_RATE_LPTX: 01838 if(Lane == DSI_CLOCK_LANE) 01839 { 01840 /* Low-Power transmission Slew Rate Compensation on Clock Lane */ 01841 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL; 01842 hdsi->Instance->WPCR[1U] |= Value<<6U; 01843 } 01844 else if(Lane == DSI_DATA_LANES) 01845 { 01846 /* Low-Power transmission Slew Rate Compensation on Data Lanes */ 01847 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; 01848 hdsi->Instance->WPCR[1U] |= Value<<8U; 01849 } 01850 else 01851 { 01852 /* Process unlocked */ 01853 __HAL_UNLOCK(hdsi); 01854 01855 return HAL_ERROR; 01856 } 01857 break; 01858 case DSI_HS_DELAY: 01859 if(Lane == DSI_CLOCK_LANE) 01860 { 01861 /* High-Speed Transmission Delay on Clock Lane */ 01862 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL; 01863 hdsi->Instance->WPCR[1U] |= Value; 01864 } 01865 else if(Lane == DSI_DATA_LANES) 01866 { 01867 /* High-Speed Transmission Delay on Data Lanes */ 01868 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; 01869 hdsi->Instance->WPCR[1U] |= Value<<2U; 01870 } 01871 else 01872 { 01873 /* Process unlocked */ 01874 __HAL_UNLOCK(hdsi); 01875 01876 return HAL_ERROR; 01877 } 01878 break; 01879 default: 01880 break; 01881 } 01882 01883 /* Process unlocked */ 01884 __HAL_UNLOCK(hdsi); 01885 01886 return HAL_OK; 01887 } 01888 01889 /** 01890 * @brief Low-Power Reception Filter Tuning 01891 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01892 * the configuration information for the DSI. 01893 * @param Frequency cutoff frequency of low-pass filter at the input of LPRX 01894 * @retval HAL status 01895 */ 01896 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) 01897 { 01898 /* Process locked */ 01899 __HAL_LOCK(hdsi); 01900 01901 /* Low-Power RX low-pass Filtering Tuning */ 01902 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT; 01903 hdsi->Instance->WPCR[1U] |= Frequency<<25U; 01904 01905 /* Process unlocked */ 01906 __HAL_UNLOCK(hdsi); 01907 01908 return HAL_OK; 01909 } 01910 01911 /** 01912 * @brief Activate an additional current path on all lanes to meet the SDDTx parameter 01913 * defined in the MIPI D-PHY specification 01914 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01915 * the configuration information for the DSI. 01916 * @param State ENABLE or DISABLE 01917 * @retval HAL status 01918 */ 01919 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) 01920 { 01921 /* Process locked */ 01922 __HAL_LOCK(hdsi); 01923 01924 /* Check function parameters */ 01925 assert_param(IS_FUNCTIONAL_STATE(State)); 01926 01927 /* Activate/Disactivate additional current path on all lanes */ 01928 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC; 01929 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U); 01930 01931 /* Process unlocked */ 01932 __HAL_UNLOCK(hdsi); 01933 01934 return HAL_OK; 01935 } 01936 01937 /** 01938 * @brief Custom lane pins configuration 01939 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01940 * the configuration information for the DSI. 01941 * @param CustomLane Function to be applyed on selected lane. 01942 * This parameter can be any value of @ref DSI_CustomLane 01943 * @param Lane select between clock or data lane 0 or data lane 1. 01944 * This parameter can be any value of @ref DSI_Lane_Select 01945 * @param State ENABLE or DISABLE 01946 * @retval HAL status 01947 */ 01948 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) 01949 { 01950 /* Process locked */ 01951 __HAL_LOCK(hdsi); 01952 01953 /* Check function parameters */ 01954 assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); 01955 assert_param(IS_DSI_LANE(Lane)); 01956 assert_param(IS_FUNCTIONAL_STATE(State)); 01957 01958 switch(CustomLane) 01959 { 01960 case DSI_SWAP_LANE_PINS: 01961 if(Lane == DSI_CLK_LANE) 01962 { 01963 /* Swap pins on clock lane */ 01964 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; 01965 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); 01966 } 01967 else if(Lane == DSI_DATA_LANE0) 01968 { 01969 /* Swap pins on data lane 0 */ 01970 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; 01971 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); 01972 } 01973 else if(Lane == DSI_DATA_LANE1) 01974 { 01975 /* Swap pins on data lane 1 */ 01976 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; 01977 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); 01978 } 01979 else 01980 { 01981 /* Process unlocked */ 01982 __HAL_UNLOCK(hdsi); 01983 01984 return HAL_ERROR; 01985 } 01986 break; 01987 case DSI_INVERT_HS_SIGNAL: 01988 if(Lane == DSI_CLK_LANE) 01989 { 01990 /* Invert HS signal on clock lane */ 01991 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; 01992 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U); 01993 } 01994 else if(Lane == DSI_DATA_LANE0) 01995 { 01996 /* Invert HS signal on data lane 0 */ 01997 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0; 01998 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U); 01999 } 02000 else if(Lane == DSI_DATA_LANE1) 02001 { 02002 /* Invert HS signal on data lane 1 */ 02003 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; 02004 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); 02005 } 02006 else 02007 { 02008 /* Process unlocked */ 02009 __HAL_UNLOCK(hdsi); 02010 02011 return HAL_ERROR; 02012 } 02013 break; 02014 default: 02015 break; 02016 } 02017 02018 /* Process unlocked */ 02019 __HAL_UNLOCK(hdsi); 02020 02021 return HAL_OK; 02022 } 02023 02024 /** 02025 * @brief Set custom timing for the PHY 02026 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02027 * the configuration information for the DSI. 02028 * @param Timing PHY timing to be adjusted. 02029 * This parameter can be any value of @ref DSI_PHY_Timing 02030 * @param State ENABLE or DISABLE 02031 * @param Value Custom value of the timing 02032 * @retval HAL status 02033 */ 02034 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) 02035 { 02036 /* Process locked */ 02037 __HAL_LOCK(hdsi); 02038 02039 /* Check function parameters */ 02040 assert_param(IS_DSI_PHY_TIMING(Timing)); 02041 assert_param(IS_FUNCTIONAL_STATE(State)); 02042 02043 switch(Timing) 02044 { 02045 case DSI_TCLK_POST: 02046 /* Enable/Disable custom timing setting */ 02047 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; 02048 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); 02049 02050 if(State != DISABLE) 02051 { 02052 /* Set custom value */ 02053 hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; 02054 hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; 02055 } 02056 02057 break; 02058 case DSI_TLPX_CLK: 02059 /* Enable/Disable custom timing setting */ 02060 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; 02061 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); 02062 02063 if(State != DISABLE) 02064 { 02065 /* Set custom value */ 02066 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; 02067 hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; 02068 } 02069 02070 break; 02071 case DSI_THS_EXIT: 02072 /* Enable/Disable custom timing setting */ 02073 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; 02074 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); 02075 02076 if(State != DISABLE) 02077 { 02078 /* Set custom value */ 02079 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; 02080 hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; 02081 } 02082 02083 break; 02084 case DSI_TLPX_DATA: 02085 /* Enable/Disable custom timing setting */ 02086 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; 02087 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); 02088 02089 if(State != DISABLE) 02090 { 02091 /* Set custom value */ 02092 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; 02093 hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; 02094 } 02095 02096 break; 02097 case DSI_THS_ZERO: 02098 /* Enable/Disable custom timing setting */ 02099 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; 02100 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); 02101 02102 if(State != DISABLE) 02103 { 02104 /* Set custom value */ 02105 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; 02106 hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; 02107 } 02108 02109 break; 02110 case DSI_THS_TRAIL: 02111 /* Enable/Disable custom timing setting */ 02112 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; 02113 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); 02114 02115 if(State != DISABLE) 02116 { 02117 /* Set custom value */ 02118 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; 02119 hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; 02120 } 02121 02122 break; 02123 case DSI_THS_PREPARE: 02124 /* Enable/Disable custom timing setting */ 02125 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; 02126 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); 02127 02128 if(State != DISABLE) 02129 { 02130 /* Set custom value */ 02131 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; 02132 hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; 02133 } 02134 02135 break; 02136 case DSI_TCLK_ZERO: 02137 /* Enable/Disable custom timing setting */ 02138 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; 02139 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); 02140 02141 if(State != DISABLE) 02142 { 02143 /* Set custom value */ 02144 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; 02145 hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; 02146 } 02147 02148 break; 02149 case DSI_TCLK_PREPARE: 02150 /* Enable/Disable custom timing setting */ 02151 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; 02152 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); 02153 02154 if(State != DISABLE) 02155 { 02156 /* Set custom value */ 02157 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; 02158 hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; 02159 } 02160 02161 break; 02162 default: 02163 break; 02164 } 02165 02166 /* Process unlocked */ 02167 __HAL_UNLOCK(hdsi); 02168 02169 return HAL_OK; 02170 } 02171 02172 /** 02173 * @brief Force the Clock/Data Lane in TX Stop Mode 02174 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02175 * the configuration information for the DSI. 02176 * @param Lane select between clock or data lanes. 02177 * This parameter can be any value of @ref DSI_Lane_Group 02178 * @param State ENABLE or DISABLE 02179 * @retval HAL status 02180 */ 02181 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) 02182 { 02183 /* Process locked */ 02184 __HAL_LOCK(hdsi); 02185 02186 /* Check function parameters */ 02187 assert_param(IS_DSI_LANE_GROUP(Lane)); 02188 assert_param(IS_FUNCTIONAL_STATE(State)); 02189 02190 if(Lane == DSI_CLOCK_LANE) 02191 { 02192 /* Force/Unforce the Clock Lane in TX Stop Mode */ 02193 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL; 02194 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U); 02195 } 02196 else if(Lane == DSI_DATA_LANES) 02197 { 02198 /* Force/Unforce the Data Lanes in TX Stop Mode */ 02199 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; 02200 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U); 02201 } 02202 else 02203 { 02204 /* Process unlocked */ 02205 __HAL_UNLOCK(hdsi); 02206 02207 return HAL_ERROR; 02208 } 02209 02210 /* Process unlocked */ 02211 __HAL_UNLOCK(hdsi); 02212 02213 return HAL_OK; 02214 } 02215 02216 /** 02217 * @brief Force LP Receiver in Low-Power Mode 02218 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02219 * the configuration information for the DSI. 02220 * @param State ENABLE or DISABLE 02221 * @retval HAL status 02222 */ 02223 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) 02224 { 02225 /* Process locked */ 02226 __HAL_LOCK(hdsi); 02227 02228 /* Check function parameters */ 02229 assert_param(IS_FUNCTIONAL_STATE(State)); 02230 02231 /* Force/Unforce LP Receiver in Low-Power Mode */ 02232 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM; 02233 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U); 02234 02235 /* Process unlocked */ 02236 __HAL_UNLOCK(hdsi); 02237 02238 return HAL_OK; 02239 } 02240 02241 /** 02242 * @brief Force Data Lanes in RX Mode after a BTA 02243 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02244 * the configuration information for the DSI. 02245 * @param State ENABLE or DISABLE 02246 * @retval HAL status 02247 */ 02248 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) 02249 { 02250 /* Process locked */ 02251 __HAL_LOCK(hdsi); 02252 02253 /* Check function parameters */ 02254 assert_param(IS_FUNCTIONAL_STATE(State)); 02255 02256 /* Force Data Lanes in RX Mode */ 02257 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL; 02258 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U); 02259 02260 /* Process unlocked */ 02261 __HAL_UNLOCK(hdsi); 02262 02263 return HAL_OK; 02264 } 02265 02266 /** 02267 * @brief Enable a pull-down on the lanes to prevent from floating states when unused 02268 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02269 * the configuration information for the DSI. 02270 * @param State ENABLE or DISABLE 02271 * @retval HAL status 02272 */ 02273 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) 02274 { 02275 /* Process locked */ 02276 __HAL_LOCK(hdsi); 02277 02278 /* Check function parameters */ 02279 assert_param(IS_FUNCTIONAL_STATE(State)); 02280 02281 /* Enable/Disable pull-down on lanes */ 02282 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN; 02283 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U); 02284 02285 /* Process unlocked */ 02286 __HAL_UNLOCK(hdsi); 02287 02288 return HAL_OK; 02289 } 02290 02291 /** 02292 * @brief Switch off the contention detection on data lanes 02293 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02294 * the configuration information for the DSI. 02295 * @param State ENABLE or DISABLE 02296 * @retval HAL status 02297 */ 02298 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) 02299 { 02300 /* Process locked */ 02301 __HAL_LOCK(hdsi); 02302 02303 /* Check function parameters */ 02304 assert_param(IS_FUNCTIONAL_STATE(State)); 02305 02306 /* Contention Detection on Data Lanes OFF */ 02307 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL; 02308 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U); 02309 02310 /* Process unlocked */ 02311 __HAL_UNLOCK(hdsi); 02312 02313 return HAL_OK; 02314 } 02315 02316 /** 02317 * @} 02318 */ 02319 02320 /** @defgroup DSI_Group4 Peripheral State and Errors functions 02321 * @brief Peripheral State and Errors functions 02322 * 02323 @verbatim 02324 =============================================================================== 02325 ##### Peripheral State and Errors functions ##### 02326 =============================================================================== 02327 [..] 02328 This subsection provides functions allowing to 02329 (+) Check the DSI state. 02330 (+) Get error code. 02331 02332 @endverbatim 02333 * @{ 02334 */ 02335 02336 /** 02337 * @brief Return the DSI state 02338 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02339 * the configuration information for the DSI. 02340 * @retval HAL state 02341 */ 02342 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) 02343 { 02344 return hdsi->State; 02345 } 02346 02347 /** 02348 * @brief Return the DSI error code 02349 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02350 * the configuration information for the DSI. 02351 * @retval DSI Error Code 02352 */ 02353 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) 02354 { 02355 /* Get the error code */ 02356 return hdsi->ErrorCode; 02357 } 02358 02359 /** 02360 * @} 02361 */ 02362 02363 /** 02364 * @} 02365 */ 02366 02367 /** 02368 * @} 02369 */ 02370 02371 #endif /* DSI */ 02372 02373 #endif /* HAL_DSI_MODULE_ENABLED */ 02374 02375 /** 02376 * @} 02377 */ 02378 02379 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/