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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_HAL_DMA_H 00038 #define __STM32F4xx_HAL_DMA_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx_hal_def.h" 00046 00047 /** @addtogroup STM32F4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup DMA 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 00057 /** @defgroup DMA_Exported_Types DMA Exported Types 00058 * @brief DMA Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief DMA Configuration Structure definition 00064 */ 00065 typedef struct 00066 { 00067 uint32_t Channel; /*!< Specifies the channel used for the specified stream. 00068 This parameter can be a value of @ref DMA_Channel_selection */ 00069 00070 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00071 from memory to memory or from peripheral to memory. 00072 This parameter can be a value of @ref DMA_Data_transfer_direction */ 00073 00074 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 00075 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 00076 00077 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 00078 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 00079 00080 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 00081 This parameter can be a value of @ref DMA_Peripheral_data_size */ 00082 00083 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 00084 This parameter can be a value of @ref DMA_Memory_data_size */ 00085 00086 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 00087 This parameter can be a value of @ref DMA_mode 00088 @note The circular buffer mode cannot be used if the memory-to-memory 00089 data transfer is configured on the selected Stream */ 00090 00091 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 00092 This parameter can be a value of @ref DMA_Priority_level */ 00093 00094 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 00095 This parameter can be a value of @ref DMA_FIFO_direct_mode 00096 @note The Direct mode (FIFO mode disabled) cannot be used if the 00097 memory-to-memory data transfer is configured on the selected stream */ 00098 00099 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 00100 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 00101 00102 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 00103 It specifies the amount of data to be transferred in a single non interruptible 00104 transaction. 00105 This parameter can be a value of @ref DMA_Memory_burst 00106 @note The burst mode is possible only if the address Increment mode is enabled. */ 00107 00108 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 00109 It specifies the amount of data to be transferred in a single non interruptible 00110 transaction. 00111 This parameter can be a value of @ref DMA_Peripheral_burst 00112 @note The burst mode is possible only if the address Increment mode is enabled. */ 00113 }DMA_InitTypeDef; 00114 00115 00116 /** 00117 * @brief HAL DMA State structures definition 00118 */ 00119 typedef enum 00120 { 00121 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 00122 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 00123 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 00124 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 00125 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ 00126 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ 00127 }HAL_DMA_StateTypeDef; 00128 00129 /** 00130 * @brief HAL DMA Error Code structure definition 00131 */ 00132 typedef enum 00133 { 00134 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 00135 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 00136 }HAL_DMA_LevelCompleteTypeDef; 00137 00138 /** 00139 * @brief HAL DMA Error Code structure definition 00140 */ 00141 typedef enum 00142 { 00143 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 00144 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 00145 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 00146 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 00147 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 00148 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 00149 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 00150 }HAL_DMA_CallbackIDTypeDef; 00151 00152 /** 00153 * @brief DMA handle Structure definition 00154 */ 00155 typedef struct __DMA_HandleTypeDef 00156 { 00157 DMA_Stream_TypeDef *Instance; /*!< Register base address */ 00158 00159 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 00160 00161 HAL_LockTypeDef Lock; /*!< DMA locking object */ 00162 00163 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 00164 00165 void *Parent; /*!< Parent object state */ 00166 00167 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 00168 00169 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 00170 00171 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 00172 00173 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 00174 00175 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 00176 00177 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ 00178 00179 __IO uint32_t ErrorCode; /*!< DMA Error code */ 00180 00181 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 00182 00183 uint32_t StreamIndex; /*!< DMA Stream Index */ 00184 00185 }DMA_HandleTypeDef; 00186 00187 /** 00188 * @} 00189 */ 00190 00191 /* Exported constants --------------------------------------------------------*/ 00192 00193 /** @defgroup DMA_Exported_Constants DMA Exported Constants 00194 * @brief DMA Exported constants 00195 * @{ 00196 */ 00197 00198 /** @defgroup DMA_Error_Code DMA Error Code 00199 * @brief DMA Error Code 00200 * @{ 00201 */ 00202 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 00203 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 00204 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ 00205 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ 00206 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00207 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 00208 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ 00209 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 00210 /** 00211 * @} 00212 */ 00213 00214 /** @defgroup DMA_Channel_selection DMA Channel selection 00215 * @brief DMA channel selection 00216 * @{ 00217 */ 00218 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ 00219 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ 00220 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ 00221 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ 00222 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ 00223 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ 00224 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ 00225 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ 00226 #if defined (DMA_SxCR_CHSEL_3) 00227 #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ 00228 #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ 00229 #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ 00230 #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ 00231 #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ 00232 #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ 00233 #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ 00234 #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ 00235 #endif /* DMA_SxCR_CHSEL_3 */ 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 00241 * @brief DMA data transfer direction 00242 * @{ 00243 */ 00244 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00245 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 00246 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 00247 /** 00248 * @} 00249 */ 00250 00251 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 00252 * @brief DMA peripheral incremented mode 00253 * @{ 00254 */ 00255 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 00256 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ 00257 /** 00258 * @} 00259 */ 00260 00261 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 00262 * @brief DMA memory incremented mode 00263 * @{ 00264 */ 00265 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 00266 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ 00267 /** 00268 * @} 00269 */ 00270 00271 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 00272 * @brief DMA peripheral data size 00273 * @{ 00274 */ 00275 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 00276 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 00277 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 00278 /** 00279 * @} 00280 */ 00281 00282 /** @defgroup DMA_Memory_data_size DMA Memory data size 00283 * @brief DMA memory data size 00284 * @{ 00285 */ 00286 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 00287 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 00288 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 00289 /** 00290 * @} 00291 */ 00292 00293 /** @defgroup DMA_mode DMA mode 00294 * @brief DMA mode 00295 * @{ 00296 */ 00297 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 00298 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 00299 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 00300 /** 00301 * @} 00302 */ 00303 00304 /** @defgroup DMA_Priority_level DMA Priority level 00305 * @brief DMA priority levels 00306 * @{ 00307 */ 00308 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ 00309 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 00310 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 00311 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 00317 * @brief DMA FIFO direct mode 00318 * @{ 00319 */ 00320 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ 00321 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 00322 /** 00323 * @} 00324 */ 00325 00326 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 00327 * @brief DMA FIFO level 00328 * @{ 00329 */ 00330 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 00331 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 00332 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 00333 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 00334 /** 00335 * @} 00336 */ 00337 00338 /** @defgroup DMA_Memory_burst DMA Memory burst 00339 * @brief DMA memory burst 00340 * @{ 00341 */ 00342 #define DMA_MBURST_SINGLE 0x00000000U 00343 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 00344 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 00345 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 00346 /** 00347 * @} 00348 */ 00349 00350 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 00351 * @brief DMA peripheral burst 00352 * @{ 00353 */ 00354 #define DMA_PBURST_SINGLE 0x00000000U 00355 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 00356 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 00357 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 00358 /** 00359 * @} 00360 */ 00361 00362 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 00363 * @brief DMA interrupts definition 00364 * @{ 00365 */ 00366 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 00367 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 00368 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 00369 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 00370 #define DMA_IT_FE 0x00000080U 00371 /** 00372 * @} 00373 */ 00374 00375 /** @defgroup DMA_flag_definitions DMA flag definitions 00376 * @brief DMA flag definitions 00377 * @{ 00378 */ 00379 #define DMA_FLAG_FEIF0_4 0x00000001U 00380 #define DMA_FLAG_DMEIF0_4 0x00000004U 00381 #define DMA_FLAG_TEIF0_4 0x00000008U 00382 #define DMA_FLAG_HTIF0_4 0x00000010U 00383 #define DMA_FLAG_TCIF0_4 0x00000020U 00384 #define DMA_FLAG_FEIF1_5 0x00000040U 00385 #define DMA_FLAG_DMEIF1_5 0x00000100U 00386 #define DMA_FLAG_TEIF1_5 0x00000200U 00387 #define DMA_FLAG_HTIF1_5 0x00000400U 00388 #define DMA_FLAG_TCIF1_5 0x00000800U 00389 #define DMA_FLAG_FEIF2_6 0x00010000U 00390 #define DMA_FLAG_DMEIF2_6 0x00040000U 00391 #define DMA_FLAG_TEIF2_6 0x00080000U 00392 #define DMA_FLAG_HTIF2_6 0x00100000U 00393 #define DMA_FLAG_TCIF2_6 0x00200000U 00394 #define DMA_FLAG_FEIF3_7 0x00400000U 00395 #define DMA_FLAG_DMEIF3_7 0x01000000U 00396 #define DMA_FLAG_TEIF3_7 0x02000000U 00397 #define DMA_FLAG_HTIF3_7 0x04000000U 00398 #define DMA_FLAG_TCIF3_7 0x08000000U 00399 /** 00400 * @} 00401 */ 00402 00403 /** 00404 * @} 00405 */ 00406 00407 /* Exported macro ------------------------------------------------------------*/ 00408 00409 /** @brief Reset DMA handle state 00410 * @param __HANDLE__ specifies the DMA handle. 00411 * @retval None 00412 */ 00413 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 00414 00415 /** 00416 * @brief Return the current DMA Stream FIFO filled level. 00417 * @param __HANDLE__ DMA handle 00418 * @retval The FIFO filling state. 00419 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 00420 * and not empty. 00421 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 00422 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 00423 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 00424 * - DMA_FIFOStatus_Empty: when FIFO is empty 00425 * - DMA_FIFOStatus_Full: when FIFO is full 00426 */ 00427 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) 00428 00429 /** 00430 * @brief Enable the specified DMA Stream. 00431 * @param __HANDLE__ DMA handle 00432 * @retval None 00433 */ 00434 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) 00435 00436 /** 00437 * @brief Disable the specified DMA Stream. 00438 * @param __HANDLE__ DMA handle 00439 * @retval None 00440 */ 00441 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) 00442 00443 /* Interrupt & Flag management */ 00444 00445 /** 00446 * @brief Return the current DMA Stream transfer complete flag. 00447 * @param __HANDLE__ DMA handle 00448 * @retval The specified transfer complete flag index. 00449 */ 00450 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 00451 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 00452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 00453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 00454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 00455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 00456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 00457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 00458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 00459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 00460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 00461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 00462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 00463 DMA_FLAG_TCIF3_7) 00464 00465 /** 00466 * @brief Return the current DMA Stream half transfer complete flag. 00467 * @param __HANDLE__ DMA handle 00468 * @retval The specified half transfer complete flag index. 00469 */ 00470 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 00471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 00472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 00473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 00474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 00475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 00476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 00477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 00478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 00479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 00480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 00481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 00482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 00483 DMA_FLAG_HTIF3_7) 00484 00485 /** 00486 * @brief Return the current DMA Stream transfer error flag. 00487 * @param __HANDLE__ DMA handle 00488 * @retval The specified transfer error flag index. 00489 */ 00490 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 00491 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 00492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 00493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 00494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 00495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 00496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 00497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 00498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 00499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 00500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 00501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 00502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 00503 DMA_FLAG_TEIF3_7) 00504 00505 /** 00506 * @brief Return the current DMA Stream FIFO error flag. 00507 * @param __HANDLE__ DMA handle 00508 * @retval The specified FIFO error flag index. 00509 */ 00510 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 00511 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 00512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 00513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 00514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 00515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 00516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 00517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 00518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 00519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 00520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 00521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 00522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 00523 DMA_FLAG_FEIF3_7) 00524 00525 /** 00526 * @brief Return the current DMA Stream direct mode error flag. 00527 * @param __HANDLE__ DMA handle 00528 * @retval The specified direct mode error flag index. 00529 */ 00530 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 00531 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 00532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 00533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 00534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 00535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 00536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 00537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 00538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 00539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 00540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 00541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 00542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 00543 DMA_FLAG_DMEIF3_7) 00544 00545 /** 00546 * @brief Get the DMA Stream pending flags. 00547 * @param __HANDLE__ DMA handle 00548 * @param __FLAG__ Get the specified flag. 00549 * This parameter can be any combination of the following values: 00550 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 00551 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 00552 * @arg DMA_FLAG_TEIFx: Transfer error flag. 00553 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 00554 * @arg DMA_FLAG_FEIFx: FIFO error flag. 00555 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 00556 * @retval The state of FLAG (SET or RESET). 00557 */ 00558 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 00559 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 00560 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 00561 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 00562 00563 /** 00564 * @brief Clear the DMA Stream pending flags. 00565 * @param __HANDLE__ DMA handle 00566 * @param __FLAG__ specifies the flag to clear. 00567 * This parameter can be any combination of the following values: 00568 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 00569 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 00570 * @arg DMA_FLAG_TEIFx: Transfer error flag. 00571 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 00572 * @arg DMA_FLAG_FEIFx: FIFO error flag. 00573 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 00574 * @retval None 00575 */ 00576 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 00577 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 00578 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 00579 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 00580 00581 /** 00582 * @brief Enable the specified DMA Stream interrupts. 00583 * @param __HANDLE__ DMA handle 00584 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 00585 * This parameter can be any combination of the following values: 00586 * @arg DMA_IT_TC: Transfer complete interrupt mask. 00587 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 00588 * @arg DMA_IT_TE: Transfer error interrupt mask. 00589 * @arg DMA_IT_FE: FIFO error interrupt mask. 00590 * @arg DMA_IT_DME: Direct mode error interrupt. 00591 * @retval None 00592 */ 00593 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 00594 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) 00595 00596 /** 00597 * @brief Disable the specified DMA Stream interrupts. 00598 * @param __HANDLE__ DMA handle 00599 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 00600 * This parameter can be any combination of the following values: 00601 * @arg DMA_IT_TC: Transfer complete interrupt mask. 00602 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 00603 * @arg DMA_IT_TE: Transfer error interrupt mask. 00604 * @arg DMA_IT_FE: FIFO error interrupt mask. 00605 * @arg DMA_IT_DME: Direct mode error interrupt. 00606 * @retval None 00607 */ 00608 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 00609 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) 00610 00611 /** 00612 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. 00613 * @param __HANDLE__ DMA handle 00614 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 00615 * This parameter can be one of the following values: 00616 * @arg DMA_IT_TC: Transfer complete interrupt mask. 00617 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 00618 * @arg DMA_IT_TE: Transfer error interrupt mask. 00619 * @arg DMA_IT_FE: FIFO error interrupt mask. 00620 * @arg DMA_IT_DME: Direct mode error interrupt. 00621 * @retval The state of DMA_IT. 00622 */ 00623 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 00624 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ 00625 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) 00626 00627 /** 00628 * @brief Writes the number of data units to be transferred on the DMA Stream. 00629 * @param __HANDLE__ DMA handle 00630 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) 00631 * Number of data items depends only on the Peripheral data format. 00632 * 00633 * @note If Peripheral data format is Bytes: number of data units is equal 00634 * to total number of bytes to be transferred. 00635 * 00636 * @note If Peripheral data format is Half-Word: number of data units is 00637 * equal to total number of bytes to be transferred / 2. 00638 * 00639 * @note If Peripheral data format is Word: number of data units is equal 00640 * to total number of bytes to be transferred / 4. 00641 * 00642 * @retval The number of remaining data units in the current DMAy Streamx transfer. 00643 */ 00644 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) 00645 00646 /** 00647 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 00648 * @param __HANDLE__ DMA handle 00649 * 00650 * @retval The number of remaining data units in the current DMA Stream transfer. 00651 */ 00652 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) 00653 00654 00655 /* Include DMA HAL Extension module */ 00656 #include "stm32f4xx_hal_dma_ex.h" 00657 00658 /* Exported functions --------------------------------------------------------*/ 00659 00660 /** @defgroup DMA_Exported_Functions DMA Exported Functions 00661 * @brief DMA Exported functions 00662 * @{ 00663 */ 00664 00665 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 00666 * @brief Initialization and de-initialization functions 00667 * @{ 00668 */ 00669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 00670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 00671 /** 00672 * @} 00673 */ 00674 00675 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 00676 * @brief I/O operation functions 00677 * @{ 00678 */ 00679 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00680 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00681 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 00682 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 00683 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 00684 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 00685 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); 00686 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 00687 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 00688 00689 /** 00690 * @} 00691 */ 00692 00693 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 00694 * @brief Peripheral State functions 00695 * @{ 00696 */ 00697 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 00698 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 00699 /** 00700 * @} 00701 */ 00702 /** 00703 * @} 00704 */ 00705 /* Private Constants -------------------------------------------------------------*/ 00706 /** @defgroup DMA_Private_Constants DMA Private Constants 00707 * @brief DMA private defines and constants 00708 * @{ 00709 */ 00710 /** 00711 * @} 00712 */ 00713 00714 /* Private macros ------------------------------------------------------------*/ 00715 /** @defgroup DMA_Private_Macros DMA Private Macros 00716 * @brief DMA private macros 00717 * @{ 00718 */ 00719 #if defined (DMA_SxCR_CHSEL_3) 00720 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ 00721 ((CHANNEL) == DMA_CHANNEL_1) || \ 00722 ((CHANNEL) == DMA_CHANNEL_2) || \ 00723 ((CHANNEL) == DMA_CHANNEL_3) || \ 00724 ((CHANNEL) == DMA_CHANNEL_4) || \ 00725 ((CHANNEL) == DMA_CHANNEL_5) || \ 00726 ((CHANNEL) == DMA_CHANNEL_6) || \ 00727 ((CHANNEL) == DMA_CHANNEL_7) || \ 00728 ((CHANNEL) == DMA_CHANNEL_8) || \ 00729 ((CHANNEL) == DMA_CHANNEL_9) || \ 00730 ((CHANNEL) == DMA_CHANNEL_10)|| \ 00731 ((CHANNEL) == DMA_CHANNEL_11)|| \ 00732 ((CHANNEL) == DMA_CHANNEL_12)|| \ 00733 ((CHANNEL) == DMA_CHANNEL_13)|| \ 00734 ((CHANNEL) == DMA_CHANNEL_14)|| \ 00735 ((CHANNEL) == DMA_CHANNEL_15)) 00736 #else 00737 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ 00738 ((CHANNEL) == DMA_CHANNEL_1) || \ 00739 ((CHANNEL) == DMA_CHANNEL_2) || \ 00740 ((CHANNEL) == DMA_CHANNEL_3) || \ 00741 ((CHANNEL) == DMA_CHANNEL_4) || \ 00742 ((CHANNEL) == DMA_CHANNEL_5) || \ 00743 ((CHANNEL) == DMA_CHANNEL_6) || \ 00744 ((CHANNEL) == DMA_CHANNEL_7)) 00745 #endif /* DMA_SxCR_CHSEL_3 */ 00746 00747 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 00748 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 00749 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 00750 00751 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 00752 00753 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 00754 ((STATE) == DMA_PINC_DISABLE)) 00755 00756 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 00757 ((STATE) == DMA_MINC_DISABLE)) 00758 00759 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 00760 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 00761 ((SIZE) == DMA_PDATAALIGN_WORD)) 00762 00763 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 00764 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 00765 ((SIZE) == DMA_MDATAALIGN_WORD )) 00766 00767 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 00768 ((MODE) == DMA_CIRCULAR) || \ 00769 ((MODE) == DMA_PFCTRL)) 00770 00771 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 00772 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 00773 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 00774 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 00775 00776 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 00777 ((STATE) == DMA_FIFOMODE_ENABLE)) 00778 00779 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 00780 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 00781 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 00782 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 00783 00784 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 00785 ((BURST) == DMA_MBURST_INC4) || \ 00786 ((BURST) == DMA_MBURST_INC8) || \ 00787 ((BURST) == DMA_MBURST_INC16)) 00788 00789 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 00790 ((BURST) == DMA_PBURST_INC4) || \ 00791 ((BURST) == DMA_PBURST_INC8) || \ 00792 ((BURST) == DMA_PBURST_INC16)) 00793 /** 00794 * @} 00795 */ 00796 00797 /* Private functions ---------------------------------------------------------*/ 00798 /** @defgroup DMA_Private_Functions DMA Private Functions 00799 * @brief DMA private functions 00800 * @{ 00801 */ 00802 /** 00803 * @} 00804 */ 00805 00806 /** 00807 * @} 00808 */ 00809 00810 /** 00811 * @} 00812 */ 00813 00814 #ifdef __cplusplus 00815 } 00816 #endif 00817 00818 #endif /* __STM32F4xx_HAL_DMA_H */ 00819 00820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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