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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dma2d.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA2D HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_HAL_DMA2D_H 00038 #define __STM32F4xx_HAL_DMA2D_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 00045 defined(STM32F469xx) || defined(STM32F479xx) 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32f4xx_hal_def.h" 00048 00049 /** @addtogroup STM32F4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup DMA2D DMA2D 00054 * @brief DMA2D HAL module driver 00055 * @{ 00056 */ 00057 00058 /* Exported types ------------------------------------------------------------*/ 00059 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 00060 * @{ 00061 */ 00062 #define MAX_DMA2D_LAYER 2U 00063 00064 /** 00065 * @brief DMA2D color Structure definition 00066 */ 00067 typedef struct 00068 { 00069 uint32_t Blue; /*!< Configures the blue value. 00070 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 00071 00072 uint32_t Green; /*!< Configures the green value. 00073 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 00074 00075 uint32_t Red; /*!< Configures the red value. 00076 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 00077 } DMA2D_ColorTypeDef; 00078 00079 /** 00080 * @brief DMA2D CLUT Structure definition 00081 */ 00082 typedef struct 00083 { 00084 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 00085 00086 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 00087 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 00088 00089 uint32_t Size; /*!< Configures the DMA2D CLUT size. 00090 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 00091 } DMA2D_CLUTCfgTypeDef; 00092 00093 /** 00094 * @brief DMA2D Init structure definition 00095 */ 00096 typedef struct 00097 { 00098 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 00099 This parameter can be one value of @ref DMA2D_Mode. */ 00100 00101 uint32_t ColorMode; /*!< Configures the color format of the output image. 00102 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 00103 00104 uint32_t OutputOffset; /*!< Specifies the Offset value. 00105 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00106 00107 } DMA2D_InitTypeDef; 00108 00109 /** 00110 * @brief DMA2D Layer structure definition 00111 */ 00112 typedef struct 00113 { 00114 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 00115 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00116 00117 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 00118 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 00119 00120 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 00121 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 00122 00123 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. 00124 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. 00125 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between 00126 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 00127 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 00128 - InputAlpha[16:23] is the red value RED[0:7] 00129 - InputAlpha[8:15] is the green value GREEN[0:7] 00130 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 00131 00132 } DMA2D_LayerCfgTypeDef; 00133 00134 /** 00135 * @brief HAL DMA2D State structures definition 00136 */ 00137 typedef enum 00138 { 00139 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 00140 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00141 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00142 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00143 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 00144 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 00145 }HAL_DMA2D_StateTypeDef; 00146 00147 /** 00148 * @brief DMA2D handle Structure definition 00149 */ 00150 typedef struct __DMA2D_HandleTypeDef 00151 { 00152 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 00153 00154 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 00155 00156 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ 00157 00158 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ 00159 00160 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 00161 00162 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 00163 00164 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 00165 00166 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 00167 } DMA2D_HandleTypeDef; 00168 /** 00169 * @} 00170 */ 00171 00172 /* Exported constants --------------------------------------------------------*/ 00173 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 00174 * @{ 00175 */ 00176 00177 /** @defgroup DMA2D_Error_Code DMA2D Error Code 00178 * @{ 00179 */ 00180 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 00181 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 00182 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 00183 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 00184 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00185 /** 00186 * @} 00187 */ 00188 00189 /** @defgroup DMA2D_Mode DMA2D Mode 00190 * @{ 00191 */ 00192 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 00193 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 00194 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 00195 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ 00196 /** 00197 * @} 00198 */ 00199 00200 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 00201 * @{ 00202 */ 00203 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 00204 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 00205 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 00206 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 00207 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 00213 * @{ 00214 */ 00215 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 00216 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 00217 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 00218 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 00219 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 00220 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 00221 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 00222 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 00223 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 00224 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 00225 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 00226 /** 00227 * @} 00228 */ 00229 00230 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 00231 * @{ 00232 */ 00233 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 00234 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 00235 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 00236 with original alpha channel value */ 00237 /** 00238 * @} 00239 */ 00240 00241 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 00242 * @{ 00243 */ 00244 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 00245 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 00246 /** 00247 * @} 00248 */ 00249 00250 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 00251 * @{ 00252 */ 00253 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 00254 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 00255 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 00256 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 00257 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 00258 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 00259 /** 00260 * @} 00261 */ 00262 00263 /** @defgroup DMA2D_Flags DMA2D Flags 00264 * @{ 00265 */ 00266 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 00267 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 00268 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 00269 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 00270 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 00271 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 00272 /** 00273 * @} 00274 */ 00275 00276 /** @defgroup DMA2D_Aliases DMA2D API Aliases 00277 * @{ 00278 */ 00279 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ 00280 /** 00281 * @} 00282 */ 00283 00284 /** 00285 * @} 00286 */ 00287 /* Exported macros ------------------------------------------------------------*/ 00288 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 00289 * @{ 00290 */ 00291 00292 /** @brief Reset DMA2D handle state 00293 * @param __HANDLE__ specifies the DMA2D handle. 00294 * @retval None 00295 */ 00296 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 00297 00298 /** 00299 * @brief Enable the DMA2D. 00300 * @param __HANDLE__ DMA2D handle 00301 * @retval None. 00302 */ 00303 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 00304 00305 /* Interrupt & Flag management */ 00306 /** 00307 * @brief Get the DMA2D pending flags. 00308 * @param __HANDLE__ DMA2D handle 00309 * @param __FLAG__ flag to check. 00310 * This parameter can be any combination of the following values: 00311 * @arg DMA2D_FLAG_CE: Configuration error flag 00312 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00313 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00314 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00315 * @arg DMA2D_FLAG_TC: Transfer complete flag 00316 * @arg DMA2D_FLAG_TE: Transfer error flag 00317 * @retval The state of FLAG. 00318 */ 00319 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 00320 00321 /** 00322 * @brief Clear the DMA2D pending flags. 00323 * @param __HANDLE__ DMA2D handle 00324 * @param __FLAG__ specifies the flag to clear. 00325 * This parameter can be any combination of the following values: 00326 * @arg DMA2D_FLAG_CE: Configuration error flag 00327 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00328 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00329 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00330 * @arg DMA2D_FLAG_TC: Transfer complete flag 00331 * @arg DMA2D_FLAG_TE: Transfer error flag 00332 * @retval None 00333 */ 00334 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 00335 00336 /** 00337 * @brief Enable the specified DMA2D interrupts. 00338 * @param __HANDLE__ DMA2D handle 00339 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 00340 * This parameter can be any combination of the following values: 00341 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00342 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00343 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00344 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00345 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00346 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00347 * @retval None 00348 */ 00349 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 00350 00351 /** 00352 * @brief Disable the specified DMA2D interrupts. 00353 * @param __HANDLE__ DMA2D handle 00354 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 00355 * This parameter can be any combination of the following values: 00356 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00357 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00358 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00359 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00360 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00361 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00362 * @retval None 00363 */ 00364 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 00365 00366 /** 00367 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 00368 * @param __HANDLE__ DMA2D handle 00369 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 00370 * This parameter can be one of the following values: 00371 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00372 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00373 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00374 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00375 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00376 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00377 * @retval The state of INTERRUPT source. 00378 */ 00379 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 00380 00381 /** 00382 * @} 00383 */ 00384 00385 /* Exported functions --------------------------------------------------------*/ 00386 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 00387 * @{ 00388 */ 00389 00390 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 00391 * @{ 00392 */ 00393 00394 /* Initialization and de-initialization functions *******************************/ 00395 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 00396 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); 00397 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); 00398 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); 00399 00400 /** 00401 * @} 00402 */ 00403 00404 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 00405 * @{ 00406 */ 00407 00408 /* IO operation functions *******************************************************/ 00409 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 00410 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 00411 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 00412 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 00413 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 00414 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 00415 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 00416 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00417 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00418 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00419 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00420 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00421 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00422 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 00423 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 00424 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 00425 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 00426 00427 /** 00428 * @} 00429 */ 00430 00431 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 00432 * @{ 00433 */ 00434 00435 /* Peripheral Control functions *************************************************/ 00436 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00437 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00438 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 00439 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00440 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00441 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 00442 00443 /** 00444 * @} 00445 */ 00446 00447 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 00448 * @{ 00449 */ 00450 00451 /* Peripheral State functions ***************************************************/ 00452 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 00453 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 00454 00455 /** 00456 * @} 00457 */ 00458 00459 /** 00460 * @} 00461 */ 00462 00463 /* Private constants ---------------------------------------------------------*/ 00464 00465 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 00466 * @{ 00467 */ 00468 00469 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 00470 * @{ 00471 */ 00472 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 00473 /** 00474 * @} 00475 */ 00476 00477 /** @defgroup DMA2D_Color_Value DMA2D Color Value 00478 * @{ 00479 */ 00480 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 00481 /** 00482 * @} 00483 */ 00484 00485 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 00486 * @{ 00487 */ 00488 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 00489 /** 00490 * @} 00491 */ 00492 00493 /** @defgroup DMA2D_Offset DMA2D Offset 00494 * @{ 00495 */ 00496 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */ 00497 /** 00498 * @} 00499 */ 00500 00501 /** @defgroup DMA2D_Size DMA2D Size 00502 * @{ 00503 */ 00504 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */ 00505 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */ 00506 /** 00507 * @} 00508 */ 00509 00510 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 00511 * @{ 00512 */ 00513 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D CLUT size */ 00514 /** 00515 * @} 00516 */ 00517 00518 /** 00519 * @} 00520 */ 00521 00522 /* Private macros ------------------------------------------------------------*/ 00523 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 00524 * @{ 00525 */ 00526 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER) 00527 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 00528 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 00529 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 00530 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 00531 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 00532 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 00533 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 00534 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 00535 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 00536 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 00537 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 00538 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ 00539 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 00540 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ 00541 ((INPUT_CM) == DMA2D_INPUT_A4)) 00542 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 00543 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 00544 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 00545 00546 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 00547 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 00548 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 00549 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 00550 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 00551 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 00552 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 00553 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 00554 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 00555 /** 00556 * @} 00557 */ 00558 00559 /** 00560 * @} 00561 */ 00562 00563 /** 00564 * @} 00565 */ 00566 00567 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 00568 00569 #ifdef __cplusplus 00570 } 00571 #endif 00572 00573 #endif /* __STM32F4xx_HAL_DMA2D_H */ 00574 00575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1