STM32F439xx HAL User Manual
stm32f4xx_hal_dma2d.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dma2d.c
00004   * @author  MCD Application Team
00005   * @brief   DMA2D HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the DMA2D peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions 
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       (#) Program the required configuration through the following parameters:
00019           the transfer mode, the output color mode and the output offset using
00020           HAL_DMA2D_Init() function.
00021 
00022       (#) Program the required configuration through the following parameters:
00023           the input color mode, the input color, the input alpha value, the alpha mode,
00024           and the input offset using HAL_DMA2D_ConfigLayer() function for foreground 
00025           or/and background layer.
00026           
00027      *** Polling mode IO operation ***
00028      =================================
00029     [..]
00030        (#) Configure pdata parameter (explained hereafter), destination and data length
00031            and enable the transfer using HAL_DMA2D_Start().
00032        (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
00033            user can specify the value of timeout according to his end application.
00034 
00035      *** Interrupt mode IO operation ***
00036      ===================================
00037      [..]
00038        (#) Configure pdata parameter, destination and data length and enable 
00039            the transfer using HAL_DMA2D_Start_IT().
00040        (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine
00041        (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
00042            add his own function by customization of function pointer XferCpltCallback (member
00043            of DMA2D handle structure).
00044        (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
00045            XferErrorCallback.
00046 
00047          -@-   In Register-to-Memory transfer mode, pdata parameter is the register
00048                color, in Memory-to-memory or Memory-to-Memory with pixel format
00049                conversion pdata is the source address.
00050 
00051          -@-   Configure the foreground source address, the background source address,
00052                the destination and data length then Enable the transfer using
00053                HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
00054                in interrupt mode
00055 
00056          -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
00057                are used if the memory to memory with blending transfer mode is selected.
00058 
00059       (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
00060           mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
00061 
00062       (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
00063 
00064       (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two 
00065           consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
00066           and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
00067           HAL_DMA2D_DisableDeadTime().
00068 
00069       (#) The transfer can be suspended, resumed and aborted using the following
00070           functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
00071 
00072       (#) The CLUT loading can be suspended, resumed and aborted using the following
00073           functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
00074           HAL_DMA2D_CLUTLoading_Abort().
00075 
00076       (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
00077       
00078       (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
00079 
00080      *** DMA2D HAL driver macros list ***
00081      =============================================
00082      [..]
00083        Below the list of most used macros in DMA2D HAL driver :
00084 
00085       (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
00086       (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
00087       (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
00088       (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
00089       (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
00090       (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not
00091 
00092      [..]
00093       (@) You can refer to the DMA2D HAL driver header file for more useful macros
00094 
00095   @endverbatim
00096   ******************************************************************************
00097   * @attention
00098   *
00099   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00100   *
00101   * Redistribution and use in source and binary forms, with or without modification,
00102   * are permitted provided that the following conditions are met:
00103   *   1. Redistributions of source code must retain the above copyright notice,
00104   *      this list of conditions and the following disclaimer.
00105   *   2. Redistributions in binary form must reproduce the above copyright notice,
00106   *      this list of conditions and the following disclaimer in the documentation
00107   *      and/or other materials provided with the distribution.
00108   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00109   *      may be used to endorse or promote products derived from this software
00110   *      without specific prior written permission.
00111   *
00112   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00113   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00114   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00115   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00116   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00117   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00118   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00119   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00120   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00121   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00122   *
00123   ******************************************************************************
00124   */
00125 
00126 /* Includes ------------------------------------------------------------------*/
00127 #include "stm32f4xx_hal.h"
00128 
00129 /** @addtogroup STM32F4xx_HAL_Driver
00130   * @{
00131   */
00132 
00133 /** @defgroup DMA2D  DMA2D
00134   * @brief DMA2D HAL module driver
00135   * @{
00136   */
00137 
00138 #ifdef HAL_DMA2D_MODULE_ENABLED
00139 
00140 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
00141 
00142 /* Private types -------------------------------------------------------------*/
00143 /* Private define ------------------------------------------------------------*/
00144 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
00145   * @{
00146   */
00147 
00148 /** @defgroup DMA2D_TimeOut DMA2D Time Out
00149   * @{
00150   */
00151 #define DMA2D_TIMEOUT_ABORT           1000U  /*!<  1s  */
00152 #define DMA2D_TIMEOUT_SUSPEND         1000U  /*!<  1s  */
00153 /**
00154   * @}
00155   */
00156 
00157 /** @defgroup DMA2D_Shifts DMA2D Shifts
00158   * @{
00159   */
00160 #define DMA2D_POSITION_FGPFCCR_CS     (uint32_t)DMA2D_FGPFCCR_CS_Pos    /*!< Required left shift to set foreground CLUT size */
00161 #define DMA2D_POSITION_BGPFCCR_CS     (uint32_t)DMA2D_BGPFCCR_CS_Pos    /*!< Required left shift to set background CLUT size */
00162 
00163 #define DMA2D_POSITION_FGPFCCR_CCM    (uint32_t)DMA2D_FGPFCCR_CCM_Pos   /*!< Required left shift to set foreground CLUT color mode */
00164 #define DMA2D_POSITION_BGPFCCR_CCM    (uint32_t)DMA2D_BGPFCCR_CCM_Pos   /*!< Required left shift to set background CLUT color mode */
00165 
00166 #define DMA2D_POSITION_AMTCR_DT       (uint32_t)DMA2D_AMTCR_DT_Pos      /*!< Required left shift to set deadtime value */
00167 
00168 #define DMA2D_POSITION_FGPFCCR_AM     (uint32_t)DMA2D_FGPFCCR_AM_Pos    /*!< Required left shift to set foreground alpha mode */
00169 #define DMA2D_POSITION_BGPFCCR_AM     (uint32_t)DMA2D_BGPFCCR_AM_Pos    /*!< Required left shift to set background alpha mode */
00170 
00171 #define DMA2D_POSITION_FGPFCCR_ALPHA  (uint32_t)DMA2D_FGPFCCR_ALPHA_Pos /*!< Required left shift to set foreground alpha value */
00172 #define DMA2D_POSITION_BGPFCCR_ALPHA  (uint32_t)DMA2D_BGPFCCR_ALPHA_Pos /*!< Required left shift to set background alpha value */
00173 
00174 #define DMA2D_POSITION_NLR_PL         (uint32_t)DMA2D_NLR_PL_Pos        /*!< Required left shift to set pixels per lines value */
00175 /**
00176   * @}
00177   */
00178 
00179 /**
00180   * @}
00181   */
00182 
00183 /* Private variables ---------------------------------------------------------*/
00184 /* Private constants ---------------------------------------------------------*/
00185 /* Private macro -------------------------------------------------------------*/
00186 /* Private function prototypes -----------------------------------------------*/
00187 /** @addtogroup DMA2D_Private_Functions_Prototypes
00188   * @{
00189   */
00190 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00191 /**
00192   * @}
00193   */
00194 
00195 /* Private functions ---------------------------------------------------------*/
00196 /* Exported functions --------------------------------------------------------*/
00197 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
00198   * @{
00199   */
00200 
00201 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
00202  *  @brief   Initialization and Configuration functions
00203  *
00204 @verbatim
00205  ===============================================================================
00206                 ##### Initialization and Configuration functions #####
00207  ===============================================================================
00208     [..]  This section provides functions allowing to:
00209       (+) Initialize and configure the DMA2D
00210       (+) De-initialize the DMA2D
00211 
00212 @endverbatim
00213   * @{
00214   */
00215 
00216 /**
00217   * @brief  Initialize the DMA2D according to the specified
00218   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
00219   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00220   *                 the configuration information for the DMA2D.
00221   * @retval HAL status
00222   */
00223 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
00224 {
00225   /* Check the DMA2D peripheral state */
00226   if(hdma2d == NULL)
00227   {
00228      return HAL_ERROR;
00229   }
00230 
00231   /* Check the parameters */
00232   assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
00233   assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
00234   assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
00235   assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
00236 
00237   if(hdma2d->State == HAL_DMA2D_STATE_RESET)
00238   {
00239     /* Allocate lock resource and initialize it */
00240     hdma2d->Lock = HAL_UNLOCKED;
00241     /* Init the low level hardware */
00242     HAL_DMA2D_MspInit(hdma2d);
00243   }
00244 
00245   /* Change DMA2D peripheral state */
00246   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00247 
00248   /* DMA2D CR register configuration -------------------------------------------*/
00249   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
00250 
00251   /* DMA2D OPFCCR register configuration ---------------------------------------*/
00252   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
00253 
00254   /* DMA2D OOR register configuration ------------------------------------------*/
00255   MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);  
00256 
00257   /* Update error code */
00258   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00259 
00260   /* Initialize the DMA2D state*/
00261   hdma2d->State  = HAL_DMA2D_STATE_READY;
00262 
00263   return HAL_OK;
00264 }
00265 
00266 /**
00267   * @brief  Deinitializes the DMA2D peripheral registers to their default reset
00268   *         values.
00269   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00270   *                 the configuration information for the DMA2D.
00271   * @retval None
00272   */
00273 
00274 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
00275 {
00276   /* Check the DMA2D peripheral state */
00277   if(hdma2d == NULL)
00278   {
00279      return HAL_ERROR;
00280   }
00281 
00282   /* Before aborting any DMA2D transfer or CLUT loading, check
00283      first whether or not DMA2D clock is enabled */
00284   if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
00285   {
00286     /* Abort DMA2D transfer if any */
00287     if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
00288     {
00289       if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
00290       {
00291         /* Issue when aborting DMA2D transfer */
00292         return HAL_ERROR;
00293       }
00294     }
00295     else
00296     {
00297       /* Abort background CLUT loading if any */
00298       if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
00299       {
00300         if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
00301         {
00302           /* Issue when aborting background CLUT loading */
00303           return HAL_ERROR;
00304         }
00305       }
00306       else
00307       {
00308         /* Abort foreground CLUT loading if any */
00309         if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
00310         {
00311           if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
00312           {
00313             /* Issue when aborting foreground CLUT loading */
00314             return HAL_ERROR;
00315           }
00316         }
00317       }
00318     }
00319   }
00320 
00321   /* Carry on with de-initialization of low level hardware */
00322   HAL_DMA2D_MspDeInit(hdma2d);
00323 
00324   /* Reset DMA2D control registers*/
00325   hdma2d->Instance->CR = 0U;
00326   hdma2d->Instance->FGOR = 0U;
00327   hdma2d->Instance->BGOR = 0U;
00328   hdma2d->Instance->FGPFCCR = 0U;
00329   hdma2d->Instance->BGPFCCR = 0U;
00330   hdma2d->Instance->OPFCCR = 0U;
00331 
00332   /* Update error code */
00333   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00334 
00335   /* Initialize the DMA2D state*/
00336   hdma2d->State  = HAL_DMA2D_STATE_RESET;
00337 
00338   /* Release Lock */
00339   __HAL_UNLOCK(hdma2d);
00340 
00341   return HAL_OK;
00342 }
00343 
00344 /**
00345   * @brief  Initializes the DMA2D MSP.
00346   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00347   *                 the configuration information for the DMA2D.
00348   * @retval None
00349   */
00350 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
00351 {
00352   /* Prevent unused argument(s) compilation warning */
00353   UNUSED(hdma2d);
00354 
00355   /* NOTE : This function should not be modified; when the callback is needed,
00356             the HAL_DMA2D_MspInit can be implemented in the user file.
00357    */
00358 }
00359 
00360 /**
00361   * @brief  DeInitializes the DMA2D MSP.
00362   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00363   *                 the configuration information for the DMA2D.
00364   * @retval None
00365   */
00366 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
00367 {
00368   /* Prevent unused argument(s) compilation warning */
00369   UNUSED(hdma2d);
00370 
00371   /* NOTE : This function should not be modified; when the callback is needed,
00372             the HAL_DMA2D_MspDeInit can be implemented in the user file.
00373    */
00374 }
00375 
00376 /**
00377   * @}
00378   */
00379 
00380 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
00381  *  @brief   IO operation functions
00382  *
00383 @verbatim
00384  ===============================================================================
00385                       #####  IO operation functions  #####
00386  ===============================================================================
00387     [..]  This section provides functions allowing to:
00388       (+) Configure the pdata, destination address and data size then
00389           start the DMA2D transfer.
00390       (+) Configure the source for foreground and background, destination address
00391           and data size then start a MultiBuffer DMA2D transfer.
00392       (+) Configure the pdata, destination address and data size then
00393           start the DMA2D transfer with interrupt.
00394       (+) Configure the source for foreground and background, destination address
00395           and data size then start a MultiBuffer DMA2D transfer with interrupt.
00396       (+) Abort DMA2D transfer.
00397       (+) Suspend DMA2D transfer.
00398       (+) Resume DMA2D transfer.
00399       (+) Enable CLUT transfer.
00400       (+) Configure CLUT loading then start transfer in polling mode.
00401       (+) Configure CLUT loading then start transfer in interrupt mode.
00402       (+) Abort DMA2D CLUT loading.
00403       (+) Suspend DMA2D CLUT loading.
00404       (+) Resume DMA2D CLUT loading.
00405       (+) Poll for transfer complete.
00406       (+) handle DMA2D interrupt request.
00407       (+) Transfer watermark callback.
00408       (+) CLUT Transfer Complete callback.
00409 
00410 @endverbatim
00411   * @{
00412   */
00413 
00414 /**
00415   * @brief  Start the DMA2D Transfer.
00416   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00417   *                     the configuration information for the DMA2D.
00418   * @param  pdata      Configure the source memory Buffer address if 
00419   *                     Memory-to-Memory or Memory-to-Memory with pixel format
00420   *                     conversion mode is selected, or configure 
00421   *                     the color value if Register-to-Memory mode is selected.
00422   * @param  DstAddress The destination memory Buffer address.
00423   * @param  Width      The width of data to be transferred from source to destination (expressed in number of pixels per line).
00424   * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
00425   * @retval HAL status
00426   */
00427 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00428 {
00429   /* Check the parameters */
00430   assert_param(IS_DMA2D_LINE(Height));
00431   assert_param(IS_DMA2D_PIXEL(Width));
00432 
00433   /* Process locked */
00434   __HAL_LOCK(hdma2d);
00435 
00436   /* Change DMA2D peripheral state */
00437   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00438 
00439   /* Configure the source, destination address and the data size */
00440   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00441 
00442   /* Enable the Peripheral */
00443   __HAL_DMA2D_ENABLE(hdma2d);
00444 
00445   return HAL_OK;
00446 }
00447 
00448 /**
00449   * @brief  Start the DMA2D Transfer with interrupt enabled.
00450   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00451   *                     the configuration information for the DMA2D.
00452   * @param  pdata      Configure the source memory Buffer address if
00453   *                     the Memory-to-Memory or Memory-to-Memory with pixel format
00454   *                     conversion mode is selected, or configure 
00455   *                     the color value if Register-to-Memory mode is selected.
00456   * @param  DstAddress The destination memory Buffer address.
00457   * @param  Width      The width of data to be transferred from source to destination (expressed in number of pixels per line).
00458   * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
00459   * @retval HAL status
00460   */
00461 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00462 {
00463   /* Check the parameters */
00464   assert_param(IS_DMA2D_LINE(Height));
00465   assert_param(IS_DMA2D_PIXEL(Width));
00466 
00467   /* Process locked */
00468   __HAL_LOCK(hdma2d);
00469 
00470   /* Change DMA2D peripheral state */
00471   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00472 
00473   /* Configure the source, destination address and the data size */
00474   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00475 
00476   /* Enable the transfer complete, transfer error and configuration error interrupts */
00477   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00478 
00479   /* Enable the Peripheral */
00480   __HAL_DMA2D_ENABLE(hdma2d);
00481 
00482   return HAL_OK;
00483 }
00484 
00485 /**
00486   * @brief  Start the multi-source DMA2D Transfer.
00487   * @param  hdma2d      Pointer to a DMA2D_HandleTypeDef structure that contains
00488   *                      the configuration information for the DMA2D.
00489   * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
00490   * @param  SrcAddress2 The source memory Buffer address for the background layer.
00491   * @param  DstAddress  The destination memory Buffer address.
00492   * @param  Width       The width of data to be transferred from source to destination (expressed in number of pixels per line).
00493   * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
00494   * @retval HAL status
00495   */
00496 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00497 {
00498   /* Check the parameters */
00499   assert_param(IS_DMA2D_LINE(Height));
00500   assert_param(IS_DMA2D_PIXEL(Width));
00501 
00502   /* Process locked */
00503   __HAL_LOCK(hdma2d);
00504 
00505   /* Change DMA2D peripheral state */
00506   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00507 
00508   /* Configure DMA2D Stream source2 address */
00509   WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
00510 
00511   /* Configure the source, destination address and the data size */
00512   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00513 
00514   /* Enable the Peripheral */
00515   __HAL_DMA2D_ENABLE(hdma2d);
00516 
00517   return HAL_OK;
00518 }
00519 
00520 /**
00521   * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
00522   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00523   *                     the configuration information for the DMA2D.
00524   * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
00525   * @param  SrcAddress2 The source memory Buffer address for the background layer.
00526   * @param  DstAddress  The destination memory Buffer address.
00527   * @param  Width       The width of data to be transferred from source to destination (expressed in number of pixels per line).
00528   * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
00529   * @retval HAL status
00530   */
00531 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00532 {
00533   /* Check the parameters */
00534   assert_param(IS_DMA2D_LINE(Height));
00535   assert_param(IS_DMA2D_PIXEL(Width));
00536 
00537   /* Process locked */
00538   __HAL_LOCK(hdma2d);
00539 
00540   /* Change DMA2D peripheral state */
00541   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00542 
00543   /* Configure DMA2D Stream source2 address */
00544   WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
00545 
00546   /* Configure the source, destination address and the data size */
00547   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00548 
00549   /* Enable the transfer complete, transfer error and configuration error interrupts */
00550   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00551 
00552   /* Enable the Peripheral */
00553   __HAL_DMA2D_ENABLE(hdma2d);
00554 
00555   return HAL_OK;
00556 }
00557 
00558 /**
00559   * @brief  Abort the DMA2D Transfer.
00560   * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
00561   *                  the configuration information for the DMA2D.
00562   * @retval HAL status
00563   */
00564 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
00565 {
00566   uint32_t tickstart = 0U;
00567 
00568   /* Abort the DMA2D transfer */
00569   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00570      between the register read and the register write by the CPU (writing 0 has no
00571      effect on START bitvalue) */
00572    MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
00573 
00574   /* Get tick */
00575   tickstart = HAL_GetTick();
00576 
00577   /* Check if the DMA2D is effectively disabled */
00578   while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
00579   {
00580     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
00581     {
00582       /* Update error code */
00583       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00584 
00585       /* Change the DMA2D state */
00586       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00587 
00588       /* Process Unlocked */
00589       __HAL_UNLOCK(hdma2d);
00590 
00591       return HAL_TIMEOUT;
00592     }
00593   }
00594 
00595   /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
00596   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00597 
00598   /* Change the DMA2D state*/
00599   hdma2d->State = HAL_DMA2D_STATE_READY;
00600 
00601   /* Process Unlocked */
00602   __HAL_UNLOCK(hdma2d);
00603 
00604   return HAL_OK;
00605 }
00606 
00607 /**
00608   * @brief  Suspend the DMA2D Transfer.
00609   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00610   *                 the configuration information for the DMA2D.
00611   * @retval HAL status
00612   */
00613 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
00614 {
00615   uint32_t tickstart = 0U;
00616 
00617   /* Suspend the DMA2D transfer */
00618   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00619      between the register read and the register write by the CPU (writing 0 has no
00620      effect on START bitvalue) */
00621   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
00622 
00623   /* Get tick */
00624   tickstart = HAL_GetTick();
00625 
00626   /* Check if the DMA2D is effectively suspended */
00627   while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
00628     && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
00629   {
00630     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
00631     {
00632       /* Update error code */
00633       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00634 
00635       /* Change the DMA2D state */
00636       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00637 
00638       return HAL_TIMEOUT;
00639     }
00640   }
00641 
00642    /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
00643   if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
00644   {
00645     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
00646   }
00647   else
00648   {
00649     /* Make sure SUSP bit is cleared since it is meaningless
00650        when no tranfer is on-going */
00651     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00652   }
00653 
00654   return HAL_OK;
00655 }
00656 
00657 /**
00658   * @brief  Resume the DMA2D Transfer.
00659   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00660   *                 the configuration information for the DMA2D.
00661   * @retval HAL status
00662   */
00663 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
00664 {
00665   /* Check the SUSP and START bits */
00666   if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
00667   {
00668     /* Ongoing transfer is suspended: change the DMA2D state before resuming */
00669     hdma2d->State = HAL_DMA2D_STATE_BUSY;
00670   }
00671 
00672   /* Resume the DMA2D transfer */
00673   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00674      between the register read and the register write by the CPU (writing 0 has no
00675      effect on START bitvalue) */
00676   CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
00677 
00678   return HAL_OK;
00679 }
00680 
00681 /**
00682   * @brief  Enable the DMA2D CLUT Transfer.
00683   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
00684   *                   the configuration information for the DMA2D.
00685   * @param  LayerIdx DMA2D Layer index.
00686   *                   This parameter can be one of the following values:
00687   *                   0(background) / 1(foreground)
00688   * @retval HAL status
00689   */
00690 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00691 {
00692   /* Check the parameters */
00693   assert_param(IS_DMA2D_LAYER(LayerIdx));
00694 
00695   /* Process locked */
00696   __HAL_LOCK(hdma2d);
00697 
00698   /* Change DMA2D peripheral state */
00699   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00700 
00701   if(LayerIdx == 0U)
00702   {
00703     /* Enable the background CLUT loading */
00704     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
00705   }
00706   else
00707   {
00708     /* Enable the foreground CLUT loading */
00709     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
00710   }
00711 
00712   return HAL_OK;
00713 }
00714 
00715 /**
00716   * @brief  Start DMA2D CLUT Loading.
00717   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
00718   *                   the configuration information for the DMA2D.
00719   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
00720   *                   the configuration information for the color look up table.
00721   * @param  LayerIdx DMA2D Layer index.
00722   *                   This parameter can be one of the following values:
00723   *                   0(background) / 1(foreground)
00724   * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
00725   * @retval HAL status
00726   */
00727 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
00728 {
00729   /* Check the parameters */
00730   assert_param(IS_DMA2D_LAYER(LayerIdx));
00731   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
00732   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
00733 
00734   /* Process locked */
00735   __HAL_LOCK(hdma2d);
00736 
00737   /* Change DMA2D peripheral state */
00738   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00739 
00740   /* Configure the CLUT of the background DMA2D layer */
00741   if(LayerIdx == 0U)
00742   {
00743     /* Write background CLUT memory address */
00744     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
00745 
00746     /* Write background CLUT size and CLUT color mode */
00747     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
00748             ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
00749 
00750     /* Enable the CLUT loading for the background */
00751     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
00752   }
00753   /* Configure the CLUT of the foreground DMA2D layer */
00754   else
00755   {
00756     /* Write foreground CLUT memory address */
00757     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
00758 
00759     /* Write foreground CLUT size and CLUT color mode */
00760     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
00761               ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
00762 
00763  /* Enable the CLUT loading for the foreground */
00764     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
00765   }
00766 
00767   return HAL_OK;
00768 }
00769 
00770 /**
00771   * @brief  Start DMA2D CLUT Loading with interrupt enabled.
00772   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
00773   *                   the configuration information for the DMA2D.
00774   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
00775   *                   the configuration information for the color look up table.
00776   * @param  LayerIdx DMA2D Layer index.
00777   *                   This parameter can be one of the following values:
00778   *                   0(background) / 1(foreground)
00779   * @retval HAL status
00780   */
00781 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
00782 {
00783   /* Check the parameters */
00784   assert_param(IS_DMA2D_LAYER(LayerIdx));
00785   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
00786   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
00787 
00788   /* Process locked */
00789   __HAL_LOCK(hdma2d);
00790 
00791   /* Change DMA2D peripheral state */
00792   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00793 
00794   /* Configure the CLUT of the background DMA2D layer */
00795   if(LayerIdx == 0U)
00796   {
00797     /* Write background CLUT memory address */
00798     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
00799 
00800     /* Write background CLUT size and CLUT color mode */
00801     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
00802             ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
00803 
00804     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
00805     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
00806 
00807     /* Enable the CLUT loading for the background */
00808     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
00809   }
00810   /* Configure the CLUT of the foreground DMA2D layer */
00811   else
00812   {
00813     /* Write foreground CLUT memory address */
00814     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
00815 
00816     /* Write foreground CLUT size and CLUT color mode */
00817     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
00818               ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
00819 
00820     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
00821     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
00822 
00823     /* Enable the CLUT loading for the foreground */
00824     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
00825   }
00826 
00827   return HAL_OK;
00828 }
00829 
00830 /**
00831   * @brief  Abort the DMA2D CLUT loading.
00832   * @param  hdma2d  Pointer to a DMA2D_HandleTypeDef structure that contains
00833   *                  the configuration information for the DMA2D.
00834   * @param  LayerIdx DMA2D Layer index.
00835   *                   This parameter can be one of the following values:
00836   *                   0(background) / 1(foreground) 
00837   * @retval HAL status
00838   */
00839 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00840 {
00841   uint32_t tickstart  = 0U;
00842   __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
00843 
00844   /* Abort the CLUT loading */
00845   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
00846 
00847   /* If foreground CLUT loading is considered, update local variables */
00848   if(LayerIdx == 1)
00849   {
00850     reg  = &(hdma2d->Instance->FGPFCCR);
00851   }
00852 
00853   /* Get tick */
00854   tickstart = HAL_GetTick();
00855 
00856   /* Check if the CLUT loading is aborted */
00857   while((*reg & DMA2D_BGPFCCR_START) != RESET)
00858   {
00859     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
00860     {
00861       /* Update error code */
00862       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00863 
00864       /* Change the DMA2D state */
00865       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00866 
00867       /* Process Unlocked */
00868       __HAL_UNLOCK(hdma2d);
00869 
00870       return HAL_TIMEOUT;
00871     }
00872   }
00873 
00874   /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
00875   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
00876 
00877   /* Change the DMA2D state*/
00878   hdma2d->State = HAL_DMA2D_STATE_READY;
00879 
00880   /* Process Unlocked */
00881   __HAL_UNLOCK(hdma2d);
00882 
00883   return HAL_OK;
00884 }
00885 
00886 /**
00887   * @brief  Suspend the DMA2D CLUT loading.
00888   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
00889   *                 the configuration information for the DMA2D.
00890   * @param  LayerIdx DMA2D Layer index.
00891   *                   This parameter can be one of the following values:
00892   *                   0(background) / 1(foreground)
00893   * @retval HAL status
00894   */
00895 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00896 {
00897   uint32_t tickstart = 0U;
00898   __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
00899 
00900   /* Suspend the CLUT loading */
00901   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00902 
00903   /* If foreground CLUT loading is considered, update local variables */
00904   if(LayerIdx == 1U)
00905   {
00906     reg  = &(hdma2d->Instance->FGPFCCR);
00907   }
00908 
00909   /* Get tick */
00910   tickstart = HAL_GetTick();
00911 
00912   /* Check if the CLUT loading is suspended */
00913   while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
00914     && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
00915   {
00916     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
00917     {
00918       /* Update error code */
00919       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00920 
00921       /* Change the DMA2D state */
00922       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00923 
00924       return HAL_TIMEOUT;
00925     }
00926   }
00927 
00928    /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
00929   if ((*reg & DMA2D_BGPFCCR_START) != RESET)
00930   {
00931     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
00932   }
00933   else
00934   {
00935     /* Make sure SUSP bit is cleared since it is meaningless
00936        when no tranfer is on-going */
00937     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00938   }
00939 
00940   return HAL_OK;
00941 }
00942 
00943 /**
00944   * @brief  Resume the DMA2D CLUT loading.
00945   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00946   *                 the configuration information for the DMA2D.
00947   * @param  LayerIdx DMA2D Layer index.
00948   *                   This parameter can be one of the following values:
00949   *                   0(background) / 1(foreground)
00950   * @retval HAL status
00951   */
00952 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00953 {
00954   /* Check the SUSP and START bits for background or foreground CLUT loading */
00955   if(LayerIdx == 0U)
00956   {
00957     /* Background CLUT loading suspension check */
00958     if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
00959       && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
00960     {
00961       /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
00962       hdma2d->State = HAL_DMA2D_STATE_BUSY;
00963     }
00964   }
00965   else
00966   {
00967     /* Foreground CLUT loading suspension check */
00968     if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
00969       && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
00970     {
00971       /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
00972       hdma2d->State = HAL_DMA2D_STATE_BUSY;
00973     }
00974   }
00975 
00976   /* Resume the CLUT loading */
00977   CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00978 
00979   return HAL_OK;
00980 }
00981 
00982 /**
00983   * @brief  Polling for transfer complete or CLUT loading.
00984   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
00985   *                 the configuration information for the DMA2D.
00986   * @param  Timeout Timeout duration
00987   * @retval HAL status
00988   */
00989 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
00990 {
00991   uint32_t tickstart = 0U;
00992   __IO uint32_t isrflags = 0x0U;
00993 
00994   /* Polling for DMA2D transfer */
00995   if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
00996   {
00997    /* Get tick */
00998    tickstart = HAL_GetTick();
00999 
01000     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
01001     {
01002       isrflags = READ_REG(hdma2d->Instance->ISR);
01003       if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
01004       {
01005         if ((isrflags & DMA2D_FLAG_CE) != RESET)
01006         {
01007           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01008         }
01009         if ((isrflags & DMA2D_FLAG_TE) != RESET)
01010         {
01011           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01012         }
01013         /* Clear the transfer and configuration error flags */
01014         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
01015 
01016         /* Change DMA2D state */
01017         hdma2d->State = HAL_DMA2D_STATE_ERROR;
01018 
01019         /* Process unlocked */
01020         __HAL_UNLOCK(hdma2d);
01021 
01022         return HAL_ERROR;
01023       }
01024       /* Check for the Timeout */
01025       if(Timeout != HAL_MAX_DELAY)
01026       {
01027         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01028         {
01029           /* Update error code */
01030           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01031 
01032           /* Change the DMA2D state */
01033           hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
01034 
01035           /* Process unlocked */
01036           __HAL_UNLOCK(hdma2d);
01037 
01038           return HAL_TIMEOUT;
01039         }
01040       }
01041     }
01042   }
01043   /* Polling for CLUT loading (foreground or background) */
01044   if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET)  ||
01045       ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
01046   {
01047     /* Get tick */
01048     tickstart = HAL_GetTick();
01049 
01050     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
01051     {
01052       isrflags = READ_REG(hdma2d->Instance->ISR);
01053       if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
01054       {
01055         if ((isrflags & DMA2D_FLAG_CAE) != RESET)
01056         {
01057           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
01058         }
01059         if ((isrflags & DMA2D_FLAG_CE) != RESET)
01060         {
01061           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01062         }
01063         if ((isrflags & DMA2D_FLAG_TE) != RESET)
01064         {
01065           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01066         }
01067         /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
01068         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
01069 
01070         /* Change DMA2D state */
01071         hdma2d->State= HAL_DMA2D_STATE_ERROR;
01072 
01073         /* Process unlocked */
01074         __HAL_UNLOCK(hdma2d);
01075 
01076         return HAL_ERROR;
01077       }
01078       /* Check for the Timeout */
01079       if(Timeout != HAL_MAX_DELAY)
01080       {
01081         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01082         {
01083           /* Update error code */
01084           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01085 
01086           /* Change the DMA2D state */
01087           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
01088 
01089           /* Process unlocked */
01090           __HAL_UNLOCK(hdma2d);
01091 
01092           return HAL_TIMEOUT;
01093         }
01094       }
01095     }
01096   }
01097 
01098   /* Clear the transfer complete and CLUT loading flags */
01099   __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
01100 
01101   /* Change DMA2D state */
01102   hdma2d->State = HAL_DMA2D_STATE_READY;
01103 
01104   /* Process unlocked */
01105   __HAL_UNLOCK(hdma2d);
01106 
01107   return HAL_OK;
01108 }
01109 /**
01110   * @brief  Handle DMA2D interrupt request.
01111   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01112   *                 the configuration information for the DMA2D.
01113   * @retval HAL status
01114   */
01115 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
01116 {
01117   uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
01118   uint32_t crflags = READ_REG(hdma2d->Instance->CR);
01119 
01120   /* Transfer Error Interrupt management ***************************************/
01121   if ((isrflags & DMA2D_FLAG_TE) != RESET)
01122   {
01123     if ((crflags & DMA2D_IT_TE) != RESET)
01124     {
01125       /* Disable the transfer Error interrupt */
01126       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
01127 
01128       /* Update error code */
01129       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01130 
01131       /* Clear the transfer error flag */
01132       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
01133 
01134       /* Change DMA2D state */
01135       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01136 
01137       /* Process Unlocked */
01138       __HAL_UNLOCK(hdma2d);
01139 
01140       if(hdma2d->XferErrorCallback != NULL)
01141       {
01142         /* Transfer error Callback */
01143         hdma2d->XferErrorCallback(hdma2d);
01144       }
01145     }
01146   }
01147   /* Configuration Error Interrupt management **********************************/
01148   if ((isrflags & DMA2D_FLAG_CE) != RESET)
01149   {
01150     if ((crflags & DMA2D_IT_CE) != RESET)
01151     {
01152       /* Disable the Configuration Error interrupt */
01153       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
01154 
01155       /* Clear the Configuration error flag */
01156       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
01157 
01158       /* Update error code */
01159       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01160 
01161       /* Change DMA2D state */
01162       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01163 
01164       /* Process Unlocked */
01165       __HAL_UNLOCK(hdma2d);
01166 
01167       if(hdma2d->XferErrorCallback != NULL)
01168       {
01169         /* Transfer error Callback */
01170         hdma2d->XferErrorCallback(hdma2d);
01171       }
01172     }
01173   }
01174   /* CLUT access Error Interrupt management ***********************************/
01175   if ((isrflags & DMA2D_FLAG_CAE) != RESET)
01176   {
01177     if ((crflags & DMA2D_IT_CAE) != RESET)
01178     {
01179       /* Disable the CLUT access error interrupt */
01180       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
01181 
01182       /* Clear the CLUT access error flag */
01183       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
01184 
01185       /* Update error code */
01186       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
01187 
01188       /* Change DMA2D state */
01189       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01190 
01191       /* Process Unlocked */
01192       __HAL_UNLOCK(hdma2d);
01193 
01194       if(hdma2d->XferErrorCallback != NULL)
01195       {
01196         /* Transfer error Callback */
01197         hdma2d->XferErrorCallback(hdma2d);
01198       }
01199     }
01200   }
01201   /* Transfer watermark Interrupt management **********************************/
01202   if ((isrflags & DMA2D_FLAG_TW) != RESET)
01203   {
01204     if ((crflags & DMA2D_IT_TW) != RESET)
01205     {
01206       /* Disable the transfer watermark interrupt */
01207       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
01208 
01209       /* Clear the transfer watermark flag */
01210       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
01211 
01212       /* Transfer watermark Callback */
01213       HAL_DMA2D_LineEventCallback(hdma2d);
01214     }
01215   }
01216   /* Transfer Complete Interrupt management ************************************/
01217   if ((isrflags & DMA2D_FLAG_TC) != RESET)
01218   {
01219     if ((crflags & DMA2D_IT_TC) != RESET)
01220     {
01221       /* Disable the transfer complete interrupt */
01222       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
01223 
01224       /* Clear the transfer complete flag */
01225       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
01226 
01227       /* Update error code */
01228       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
01229 
01230       /* Change DMA2D state */
01231       hdma2d->State = HAL_DMA2D_STATE_READY;
01232 
01233       /* Process Unlocked */
01234       __HAL_UNLOCK(hdma2d);
01235 
01236       if(hdma2d->XferCpltCallback != NULL)
01237       {
01238         /* Transfer complete Callback */
01239         hdma2d->XferCpltCallback(hdma2d);
01240       }
01241     }
01242   }
01243   /* CLUT Transfer Complete Interrupt management ******************************/
01244   if ((isrflags & DMA2D_FLAG_CTC) != RESET)
01245   {
01246     if ((crflags & DMA2D_IT_CTC) != RESET)
01247     {
01248       /* Disable the CLUT transfer complete interrupt */
01249       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
01250 
01251       /* Clear the CLUT transfer complete flag */
01252       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
01253 
01254       /* Update error code */
01255       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
01256 
01257       /* Change DMA2D state */
01258       hdma2d->State = HAL_DMA2D_STATE_READY;
01259 
01260       /* Process Unlocked */
01261       __HAL_UNLOCK(hdma2d);
01262 
01263       /* CLUT Transfer complete Callback */
01264       HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
01265     }
01266   }
01267 }
01268 
01269 /**
01270   * @brief  Transfer watermark callback.
01271   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01272   *                 the configuration information for the DMA2D.
01273   * @retval None
01274   */
01275 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
01276 {
01277   /* Prevent unused argument(s) compilation warning */
01278   UNUSED(hdma2d);
01279 
01280   /* NOTE : This function should not be modified; when the callback is needed,
01281             the HAL_DMA2D_LineEventCallback can be implemented in the user file.
01282    */
01283 }
01284 
01285 /**
01286   * @brief  CLUT Transfer Complete callback.
01287   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01288   *                 the configuration information for the DMA2D.
01289   * @retval None
01290   */
01291 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
01292 {
01293   /* Prevent unused argument(s) compilation warning */
01294   UNUSED(hdma2d);
01295 
01296   /* NOTE : This function should not be modified; when the callback is needed,
01297             the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
01298    */
01299 }
01300 
01301 /**
01302   * @}
01303   */
01304 
01305 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
01306  *  @brief    Peripheral Control functions 
01307  *
01308 @verbatim
01309  ===============================================================================
01310                     ##### Peripheral Control functions #####
01311  ===============================================================================
01312     [..]  This section provides functions allowing to:
01313       (+) Configure the DMA2D foreground or background layer parameters.
01314       (+) Configure the DMA2D CLUT transfer.
01315       (+) Configure the line watermark
01316       (+) Configure the dead time value.
01317       (+) Enable or disable the dead time value functionality.
01318 
01319 @endverbatim
01320   * @{
01321   */
01322 
01323 /**
01324   * @brief  Configure the DMA2D Layer according to the specified
01325   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
01326   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01327   *                 the configuration information for the DMA2D.
01328   * @param  LayerIdx DMA2D Layer index.
01329   *                   This parameter can be one of the following values:
01330   *                   0(background) / 1(foreground)
01331   * @retval HAL status
01332   */
01333 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01334 {
01335   DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
01336   uint32_t regValue = 0U;
01337 
01338   /* Check the parameters */
01339   assert_param(IS_DMA2D_LAYER(LayerIdx));
01340   assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
01341   if(hdma2d->Init.Mode != DMA2D_R2M)
01342   {
01343     assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
01344     if(hdma2d->Init.Mode != DMA2D_M2M)
01345     {
01346       assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
01347     }
01348   }
01349 
01350   /* Process locked */
01351   __HAL_LOCK(hdma2d);
01352 
01353   /* Change DMA2D peripheral state */
01354   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01355 
01356   /* DMA2D BGPFCR register configuration -----------------------------------*/
01357   /* Prepare the value to be written to the BGPFCCR register */
01358 
01359   if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01360   {
01361     regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
01362   }
01363   else
01364   {
01365     regValue =  pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
01366   }
01367   
01368   /* Configure the background DMA2D layer */
01369   if(LayerIdx == 0)
01370   {
01371     /* Write DMA2D BGPFCCR register */
01372     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
01373 
01374     /* DMA2D BGOR register configuration -------------------------------------*/
01375     WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
01376 
01377     /* DMA2D BGCOLR register configuration -------------------------------------*/
01378     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01379     {
01380       WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
01381     }
01382   }
01383   /* Configure the foreground DMA2D layer */
01384   else
01385   {
01386      /* Write DMA2D FGPFCCR register */
01387     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA), regValue);
01388 
01389     /* DMA2D FGOR register configuration -------------------------------------*/
01390     WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
01391 
01392     /* DMA2D FGCOLR register configuration -------------------------------------*/
01393     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01394     {
01395       WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
01396     }
01397   }
01398   /* Initialize the DMA2D state*/
01399   hdma2d->State = HAL_DMA2D_STATE_READY;
01400 
01401   /* Process unlocked */
01402   __HAL_UNLOCK(hdma2d);
01403 
01404   return HAL_OK;
01405 }
01406 
01407 /**
01408   * @brief  Configure the DMA2D CLUT Transfer.
01409   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
01410   *                   the configuration information for the DMA2D.
01411   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
01412   *                   the configuration information for the color look up table.
01413   * @param  LayerIdx DMA2D Layer index.
01414   *                   This parameter can be one of the following values:
01415   *                   0(background) / 1(foreground)
01416   * @retval HAL status
01417   */
01418 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01419 {
01420   /* Check the parameters */
01421   assert_param(IS_DMA2D_LAYER(LayerIdx));
01422   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01423   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01424 
01425   /* Process locked */
01426   __HAL_LOCK(hdma2d);
01427 
01428   /* Change DMA2D peripheral state */
01429   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01430 
01431   /* Configure the CLUT of the background DMA2D layer */
01432   if(LayerIdx == 0U)
01433   {
01434     /* Write background CLUT memory address */
01435     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
01436 
01437     /* Write background CLUT size and CLUT color mode */
01438     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
01439               ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
01440  }
01441  /* Configure the CLUT of the foreground DMA2D layer */
01442  else
01443  {
01444    /* Write foreground CLUT memory address */
01445     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
01446 
01447     /* Write foreground CLUT size and CLUT color mode */
01448     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
01449               ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
01450   }
01451 
01452   /* Set the DMA2D state to Ready */
01453   hdma2d->State = HAL_DMA2D_STATE_READY;
01454 
01455   /* Process unlocked */
01456   __HAL_UNLOCK(hdma2d);
01457 
01458   return HAL_OK;
01459 }
01460 
01461 /**
01462   * @brief  Configure the line watermark.
01463   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01464   *                 the configuration information for the DMA2D.
01465   * @param  Line   Line Watermark configuration (maximum 16-bit long value expected).
01466   * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
01467   * @note   The transfer watermark interrupt is disabled once it has occurred.
01468   * @retval HAL status
01469   */
01470 
01471 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
01472 {
01473   /* Check the parameters */
01474   assert_param(IS_DMA2D_LINEWATERMARK(Line));
01475 
01476   if (Line > DMA2D_LWR_LW)
01477   {
01478     return HAL_ERROR;
01479   }
01480   else
01481   {
01482     /* Process locked */
01483     __HAL_LOCK(hdma2d);
01484 
01485     /* Change DMA2D peripheral state */
01486     hdma2d->State = HAL_DMA2D_STATE_BUSY;
01487 
01488     /* Sets the Line watermark configuration */
01489     WRITE_REG(hdma2d->Instance->LWR, Line);
01490 
01491     /* Enable the Line interrupt */
01492     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
01493 
01494     /* Initialize the DMA2D state */
01495     hdma2d->State = HAL_DMA2D_STATE_READY;
01496 
01497     /* Process unlocked */
01498     __HAL_UNLOCK(hdma2d);
01499 
01500     return HAL_OK;
01501   }
01502 }
01503 
01504 /**
01505   * @brief Enable DMA2D dead time feature.
01506   * @param hdma2d DMA2D handle.
01507   * @retval HAL status
01508   */
01509 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
01510 {
01511   /* Process Locked */
01512   __HAL_LOCK(hdma2d);
01513 
01514   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01515 
01516   /* Set DMA2D_AMTCR EN bit */
01517   SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
01518 
01519   hdma2d->State = HAL_DMA2D_STATE_READY;
01520 
01521   /* Process Unlocked */
01522   __HAL_UNLOCK(hdma2d);
01523 
01524   return HAL_OK;
01525 }
01526 
01527 /**
01528   * @brief Disable DMA2D dead time feature.
01529   * @param hdma2d DMA2D handle.
01530   * @retval HAL status
01531   */
01532 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
01533 {
01534   /* Process Locked */
01535   __HAL_LOCK(hdma2d);
01536 
01537   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01538 
01539   /* Clear DMA2D_AMTCR EN bit */
01540   CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
01541 
01542   hdma2d->State = HAL_DMA2D_STATE_READY;
01543 
01544   /* Process Unlocked */
01545   __HAL_UNLOCK(hdma2d);
01546 
01547   return HAL_OK;
01548 }
01549 
01550 /**
01551   * @brief Configure dead time.
01552   * @note The dead time value represents the guaranteed minimum number of cycles between
01553   *       two consecutive transactions on the AHB bus.
01554   * @param hdma2d DMA2D handle.
01555   * @param DeadTime dead time value.
01556   * @retval HAL status
01557   */
01558 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
01559 {
01560   /* Process Locked */
01561   __HAL_LOCK(hdma2d);
01562 
01563   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01564 
01565   /* Set DMA2D_AMTCR DT field */
01566   MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
01567 
01568   hdma2d->State = HAL_DMA2D_STATE_READY;
01569 
01570   /* Process Unlocked */
01571   __HAL_UNLOCK(hdma2d);
01572 
01573   return HAL_OK;
01574 }
01575 
01576 /**
01577   * @}
01578   */
01579 
01580 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
01581  *  @brief    Peripheral State functions 
01582  *
01583 @verbatim
01584  ===============================================================================
01585                   ##### Peripheral State and Errors functions #####
01586  ===============================================================================  
01587     [..]
01588     This subsection provides functions allowing to :
01589       (+) Get the DMA2D state
01590       (+) Get the DMA2D error code
01591 
01592 @endverbatim
01593   * @{
01594   */ 
01595 
01596 /**
01597   * @brief  Return the DMA2D state
01598   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01599   *                 the configuration information for the DMA2D.
01600   * @retval HAL state
01601   */
01602 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
01603 {
01604   return hdma2d->State;
01605 }
01606 
01607 /**
01608   * @brief  Return the DMA2D error code
01609   * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
01610   *               the configuration information for DMA2D.
01611   * @retval DMA2D Error Code
01612   */
01613 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
01614 {
01615   return hdma2d->ErrorCode;
01616 }
01617 
01618 /**
01619   * @}
01620   */
01621   
01622 /**
01623   * @}
01624   */
01625 
01626 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
01627   * @{
01628   */
01629 
01630 /**
01631   * @brief  Set the DMA2D transfer parameters.
01632   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
01633   *                     the configuration information for the specified DMA2D.
01634   * @param  pdata      The source memory Buffer address
01635   * @param  DstAddress The destination memory Buffer address
01636   * @param  Width      The width of data to be transferred from source to destination.
01637   * @param  Height     The height of data to be transferred from source to destination.
01638   * @retval HAL status
01639   */
01640 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
01641 {
01642   uint32_t tmp = 0U;
01643   uint32_t tmp1 = 0U;
01644   uint32_t tmp2 = 0U;
01645   uint32_t tmp3 = 0U;
01646   uint32_t tmp4 = 0U;
01647 
01648   /* Configure DMA2D data size */
01649   MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
01650 
01651   /* Configure DMA2D destination address */
01652   WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
01653 
01654   /* Register to memory DMA2D mode selected */
01655   if (hdma2d->Init.Mode == DMA2D_R2M)
01656   {
01657     tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
01658     tmp2 = pdata & DMA2D_OCOLR_RED_1;
01659     tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
01660     tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
01661 
01662     /* Prepare the value to be written to the OCOLR register according to the color mode */
01663     if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
01664     {
01665       tmp = (tmp3 | tmp2 | tmp1| tmp4);
01666     }
01667     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
01668     {
01669       tmp = (tmp3 | tmp2 | tmp4);
01670     }
01671     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
01672     {
01673       tmp2 = (tmp2 >> 19U);
01674       tmp3 = (tmp3 >> 10U);
01675       tmp4 = (tmp4 >> 3U);
01676       tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
01677     }
01678     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
01679     {
01680       tmp1 = (tmp1 >> 31U);
01681       tmp2 = (tmp2 >> 19U);
01682       tmp3 = (tmp3 >> 11U);
01683       tmp4 = (tmp4 >> 3U);
01684       tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
01685     }
01686     else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
01687     {
01688       tmp1 = (tmp1 >> 28U);
01689       tmp2 = (tmp2 >> 20U);
01690       tmp3 = (tmp3 >> 12U);
01691       tmp4 = (tmp4 >> 4U);
01692       tmp  = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
01693     }
01694     /* Write to DMA2D OCOLR register */
01695     WRITE_REG(hdma2d->Instance->OCOLR, tmp);
01696   }
01697   else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
01698   {
01699     /* Configure DMA2D source address */
01700     WRITE_REG(hdma2d->Instance->FGMAR, pdata);
01701   }
01702 }
01703 
01704 /**
01705   * @}
01706   */
01707 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
01708 #endif /* HAL_DMA2D_MODULE_ENABLED */
01709 /**
01710   * @}
01711   */
01712 
01713 /**
01714   * @}
01715   */
01716 
01717 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/