STM32F439xx HAL User Manual
stm32f4xx_hal_dfsdm.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f4xx_hal_dfsdm.h
00004   * @author  MCD Application Team
00005   * @brief   Header file of DFSDM HAL module.
00006   ******************************************************************************
00007   * @attention
00008   *
00009   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00010   *
00011   * Redistribution and use in source and binary forms, with or without modification,
00012   * are permitted provided that the following conditions are met:
00013   *   1. Redistributions of source code must retain the above copyright notice,
00014   *      this list of conditions and the following disclaimer.
00015   *   2. Redistributions in binary form must reproduce the above copyright notice,
00016   *      this list of conditions and the following disclaimer in the documentation
00017   *      and/or other materials provided with the distribution.
00018   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00019   *      may be used to endorse or promote products derived from this software
00020   *      without specific prior written permission.
00021   *
00022   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00023   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00024   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00025   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00026   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00027   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00028   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00029   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00030   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00031   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00032   *
00033   ******************************************************************************
00034   */
00035 
00036 /* Define to prevent recursive inclusion -------------------------------------*/
00037 #ifndef __STM32F4xx_HAL_DFSDM_H
00038 #define __STM32F4xx_HAL_DFSDM_H
00039 
00040 #ifdef __cplusplus
00041  extern "C" {
00042 #endif
00043 
00044 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
00045 /* Includes ------------------------------------------------------------------*/
00046 #include "stm32f4xx_hal_def.h"
00047 
00048 /** @addtogroup STM32F4xx_HAL_Driver
00049   * @{
00050   */
00051 
00052 /** @addtogroup DFSDM
00053   * @{
00054   */ 
00055 
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
00058   * @{
00059   */
00060 
00061 /** 
00062   * @brief  HAL DFSDM Channel states definition  
00063   */ 
00064 typedef enum
00065 {
00066   HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
00067   HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
00068   HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */
00069 }HAL_DFSDM_Channel_StateTypeDef;
00070 
00071 /** 
00072   * @brief  DFSDM channel output clock structure definition  
00073   */  
00074 typedef struct
00075 {
00076   FunctionalState Activation; /*!< Output clock enable/disable */
00077   uint32_t        Selection;  /*!< Output clock is system clock or audio clock.
00078                                    This parameter can be a value of @ref DFSDM_Channel_OuputClock */
00079   uint32_t        Divider;    /*!< Output clock divider.
00080                                    This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
00081 }DFSDM_Channel_OutputClockTypeDef;
00082 
00083 /** 
00084   * @brief  DFSDM channel input structure definition  
00085   */  
00086 typedef struct
00087 {
00088   uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
00089                              This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
00090   uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
00091                              This parameter can be a value of @ref DFSDM_Channel_DataPacking */
00092   uint32_t Pins;        /*!< Input pins are taken from same or following channel.
00093                              This parameter can be a value of @ref DFSDM_Channel_InputPins */
00094 }DFSDM_Channel_InputTypeDef;
00095 
00096 /** 
00097   * @brief  DFSDM channel serial interface structure definition  
00098   */  
00099 typedef struct
00100 {
00101   uint32_t Type;     /*!< SPI or Manchester modes.
00102                           This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
00103   uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
00104                           This parameter can be a value of @ref DFSDM_Channel_SpiClock */
00105 }DFSDM_Channel_SerialInterfaceTypeDef;
00106 
00107 /** 
00108   * @brief  DFSDM channel analog watchdog structure definition  
00109   */  
00110 typedef struct
00111 {
00112   uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.
00113                               This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
00114   uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
00115                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
00116 }DFSDM_Channel_AwdTypeDef;
00117 
00118 /** 
00119   * @brief  DFSDM channel init structure definition  
00120   */  
00121 typedef struct
00122 {
00123   DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */
00124   DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */
00125   DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
00126   DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */
00127   int32_t                              Offset;          /*!< DFSDM channel offset.
00128                                                              This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00129   uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
00130                                                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
00131 }DFSDM_Channel_InitTypeDef;
00132 
00133 /** 
00134   * @brief  DFSDM channel handle structure definition  
00135   */  
00136 typedef struct
00137 {
00138   DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
00139   DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
00140   HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
00141 }DFSDM_Channel_HandleTypeDef;
00142 
00143 /** 
00144   * @brief  HAL DFSDM Filter states definition  
00145   */ 
00146 typedef enum
00147 {
00148   HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */
00149   HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */
00150   HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */
00151   HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */
00152   HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
00153   HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */
00154 }HAL_DFSDM_Filter_StateTypeDef;
00155 
00156 /** 
00157   * @brief  DFSDM filter regular conversion parameters structure definition  
00158   */  
00159 typedef struct
00160 {
00161   uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.
00162                                  This parameter can be a value of @ref DFSDM_Filter_Trigger */
00163   FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
00164   FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
00165 }DFSDM_Filter_RegularParamTypeDef;
00166 
00167 /** 
00168   * @brief  DFSDM filter injected conversion parameters structure definition  
00169   */  
00170 typedef struct
00171 {
00172   uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.
00173                                        This parameter can be a value of @ref DFSDM_Filter_Trigger */
00174   FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */
00175   FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */
00176   uint32_t        ExtTrigger;     /*!< External trigger.
00177                                        This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
00178   uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
00179                                        This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
00180 }DFSDM_Filter_InjectedParamTypeDef;
00181 
00182 /** 
00183   * @brief  DFSDM filter parameters structure definition  
00184   */  
00185 typedef struct
00186 {
00187   uint32_t SincOrder;       /*!< Sinc filter order.
00188                                  This parameter can be a value of @ref DFSDM_Filter_SincOrder */
00189   uint32_t Oversampling;    /*!< Filter oversampling ratio.
00190                                  This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
00191   uint32_t IntOversampling; /*!< Integrator oversampling ratio.
00192                                  This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
00193 }DFSDM_Filter_FilterParamTypeDef;
00194 
00195 /** 
00196   * @brief  DFSDM filter init structure definition  
00197   */  
00198 typedef struct
00199 {
00200   DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
00201   DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
00202   DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
00203 }DFSDM_Filter_InitTypeDef;
00204 
00205 /** 
00206   * @brief  DFSDM filter handle structure definition  
00207   */  
00208 typedef struct
00209 {
00210   DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
00211   DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
00212   DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */
00213   DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */
00214   uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */
00215   uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */
00216   uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */
00217   uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
00218   FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */
00219   uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */
00220   uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
00221   HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
00222   uint32_t                      ErrorCode;           /*!< DFSDM filter error code */  
00223 }DFSDM_Filter_HandleTypeDef;
00224 
00225 /** 
00226   * @brief  DFSDM filter analog watchdog parameters structure definition  
00227   */  
00228 typedef struct
00229 {
00230   uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.
00231                                  This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
00232   uint32_t Channel;         /*!< Analog watchdog channel selection.
00233                                  This parameter can be a values combination of @ref DFSDM_Channel_Selection */
00234   int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.
00235                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00236   int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.
00237                                  This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
00238   uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
00239                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
00240   uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
00241                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
00242 }DFSDM_Filter_AwdParamTypeDef;
00243 
00244 /**
00245   * @}
00246   */ 
00247 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)  
00248 /** 
00249   * @brief  Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices  
00250   */  
00251 typedef struct
00252 {
00253   uint32_t  DFSDM1ClockIn;            /*!< Source selection for DFSDM1_Ckin.
00254                                           This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/
00255   uint32_t  DFSDM2ClockIn;            /*!< Source selection for DFSDM2_Ckin.
00256                                           This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/
00257   uint32_t  DFSDM1ClockOut;            /*!< Source selection for DFSDM1_Ckout.
00258                                           This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/
00259   uint32_t  DFSDM2ClockOut;            /*!< Source selection for DFSDM2_Ckout.
00260                                           This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/
00261   uint32_t  DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2.
00262                                           This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION 
00263                                          @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2 
00264                                          @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */
00265   uint32_t  DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4.
00266                                           This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION 
00267                                          @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4 
00268                                          @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5 
00269                                          @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6 
00270                                          @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */                                                   
00271   uint32_t  DFSDM1DataDistribution;   /*!< Source selection for DatIn0 and DatIn2 of DFSDM1.
00272                                          This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */
00273   uint32_t  DFSDM2DataDistribution;  /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2.
00274                                          This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */
00275 }DFSDM_MultiChannelConfigTypeDef;
00276 #endif  /* SYSCFG_MCHDLYCR_BSCKSEL */
00277 /**
00278   * @}
00279   */ 
00280   
00281 /* End of exported types -----------------------------------------------------*/
00282 
00283 /* Exported constants --------------------------------------------------------*/
00284 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
00285   * @{
00286   */
00287 
00288 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
00289   * @{
00290   */
00291 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    0x00000000U             /*!< Source for ouput clock is system clock */
00292 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC  /*!< Source for ouput clock is audio clock */
00293 /**
00294   * @}
00295   */
00296 
00297 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
00298   * @{
00299   */
00300 #define DFSDM_CHANNEL_EXTERNAL_INPUTS        0x00000000U             /*!< Data are taken from external inputs */
00301 #define DFSDM_CHANNEL_INTERNAL_REGISTER      DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */
00302 /**
00303   * @}
00304   */
00305 
00306 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
00307   * @{
00308   */
00309 #define DFSDM_CHANNEL_STANDARD_MODE          0x00000000U             /*!< Standard data packing mode */
00310 #define DFSDM_CHANNEL_INTERLEAVED_MODE       DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
00311 #define DFSDM_CHANNEL_DUAL_MODE              DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
00312 /**
00313   * @}
00314   */
00315 
00316 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
00317   * @{
00318   */
00319 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS      0x00000000U             /*!< Input from pins on same channel */
00320 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL   /*!< Input from pins on following channel */
00321 /**
00322   * @}
00323   */
00324 
00325 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
00326   * @{
00327   */
00328 #define DFSDM_CHANNEL_SPI_RISING             0x00000000U             /*!< SPI with rising edge */
00329 #define DFSDM_CHANNEL_SPI_FALLING            DFSDM_CHCFGR1_SITP_0    /*!< SPI with falling edge */
00330 #define DFSDM_CHANNEL_MANCHESTER_RISING      DFSDM_CHCFGR1_SITP_1    /*!< Manchester with rising edge */
00331 #define DFSDM_CHANNEL_MANCHESTER_FALLING     DFSDM_CHCFGR1_SITP      /*!< Manchester with falling edge */
00332 /**
00333   * @}
00334   */
00335 
00336 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
00337   * @{
00338   */
00339 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              0x00000000U              /*!< External SPI clock */
00340 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
00341 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
00342 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */
00343 /**
00344   * @}
00345   */
00346 
00347 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
00348   * @{
00349   */
00350 #define DFSDM_CHANNEL_FASTSINC_ORDER         0x00000000U              /*!< FastSinc filter type */
00351 #define DFSDM_CHANNEL_SINC1_ORDER            DFSDM_CHAWSCDR_AWFORD_0  /*!< Sinc 1 filter type */
00352 #define DFSDM_CHANNEL_SINC2_ORDER            DFSDM_CHAWSCDR_AWFORD_1  /*!< Sinc 2 filter type */
00353 #define DFSDM_CHANNEL_SINC3_ORDER            DFSDM_CHAWSCDR_AWFORD    /*!< Sinc 3 filter type */
00354 /**
00355   * @}
00356   */
00357 
00358 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
00359   * @{
00360   */
00361 #define DFSDM_FILTER_SW_TRIGGER              0x00000000U              /*!< Software trigger */
00362 #define DFSDM_FILTER_SYNC_TRIGGER            0x00000001U              /*!< Synchronous with DFSDM_FLT0 */
00363 #define DFSDM_FILTER_EXT_TRIGGER             0x00000002U              /*!< External trigger (only for injected conversion) */
00364 /**
00365   * @}
00366   */
00367 
00368 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
00369   * @{
00370   */
00371 #if defined(STM32F413xx) || defined(STM32F423xx) 
00372 /* Trigger for stm32f413xx and STM32f423xx devices */
00373 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For All DFSDM1/2 filters */
00374 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_0                            /*!< For All DFSDM1/2 filters */
00375 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For All DFSDM1/2 filters */
00376 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */
00377 #define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM2 filter 3 */
00378 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */
00379 #define DFSDM_FILTER_EXT_TRIG_TIM11_OC1  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM2 filter 3 */
00380 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 */
00381 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM2 filter 2 and 3*/
00382 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For All DFSDM1/2 filters */
00383 #define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For All DFSDM1/2 filters */
00384 #else
00385 /* Trigger for stm32f412xx devices */
00386 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U                                       /*!< For DFSDM1 filter 0 and 1*/
00387 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM1 filter 0 and 1*/
00388 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM1 filter 0 and 1*/
00389 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1*/
00390 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM1 filter 0 and 1*/
00391 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/
00392 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/
00393 #define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL                              /*!< For DFSDM1 filter 0 and 1*/
00394 #endif
00395 /**
00396   * @}
00397   */
00398   
00399 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
00400   * @{
00401   */
00402 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0    /*!< External rising edge */
00403 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1    /*!< External falling edge */
00404 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN      /*!< External rising and falling edges */
00405 /**
00406   * @}
00407   */
00408 
00409 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
00410   * @{
00411   */
00412 #define DFSDM_FILTER_FASTSINC_ORDER        0x00000000U                                 /*!< FastSinc filter type */
00413 #define DFSDM_FILTER_SINC1_ORDER           DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */
00414 #define DFSDM_FILTER_SINC2_ORDER           DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */
00415 #define DFSDM_FILTER_SINC3_ORDER           (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
00416 #define DFSDM_FILTER_SINC4_ORDER           DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */
00417 #define DFSDM_FILTER_SINC5_ORDER           (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
00418 /**
00419   * @}
00420   */
00421 
00422 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
00423   * @{
00424   */
00425 #define DFSDM_FILTER_AWD_FILTER_DATA       0x00000000U             /*!< From digital filter */
00426 #define DFSDM_FILTER_AWD_CHANNEL_DATA      DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */
00427 /**
00428   * @}
00429   */
00430 
00431 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
00432   * @{
00433   */ 
00434 #define DFSDM_FILTER_ERROR_NONE             0x00000000U            /*!< No error */
00435 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U            /*!< Overrun occurs during regular conversion */
00436 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U            /*!< Overrun occurs during injected conversion */
00437 #define DFSDM_FILTER_ERROR_DMA              0x00000003U            /*!< DMA error occurs */
00438 /**
00439   * @}
00440   */
00441 
00442 /** @defgroup DFSDM_BreakSignals DFSDM break signals
00443   * @{
00444   */
00445 #define DFSDM_NO_BREAK_SIGNAL               0x00000000U            /*!< No break signal */
00446 #define DFSDM_BREAK_SIGNAL_0                0x00000001U            /*!< Break signal 0 */
00447 #define DFSDM_BREAK_SIGNAL_1                0x00000002U            /*!< Break signal 1 */
00448 #define DFSDM_BREAK_SIGNAL_2                0x00000004U            /*!< Break signal 2 */
00449 #define DFSDM_BREAK_SIGNAL_3                0x00000008U            /*!< Break signal 3 */
00450 /**
00451   * @}
00452   */
00453 
00454 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
00455   * @{
00456   */
00457 /* DFSDM Channels ------------------------------------------------------------*/
00458 /* The DFSDM channels are defined as follows:
00459    - in 16-bit LSB the channel mask is set
00460    - in 16-bit MSB the channel number is set
00461    e.g. for channel 3 definition:
00462         - the channel mask is 0x00000008 (bit 3 is set)
00463         - the channel number 3 is 0x00030000 
00464         --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */
00465 #define DFSDM_CHANNEL_0                     0x00000001U
00466 #define DFSDM_CHANNEL_1                     0x00010002U
00467 #define DFSDM_CHANNEL_2                     0x00020004U
00468 #define DFSDM_CHANNEL_3                     0x00030008U
00469 #define DFSDM_CHANNEL_4                     0x00040010U            /* only for stmm32f413xx and stm32f423xx devices */
00470 #define DFSDM_CHANNEL_5                     0x00050020U            /* only for stmm32f413xx and stm32f423xx devices */
00471 #define DFSDM_CHANNEL_6                     0x00060040U            /* only for stmm32f413xx and stm32f423xx devices */
00472 #define DFSDM_CHANNEL_7                     0x00070080U            /* only for stmm32f413xx and stm32f423xx devices */
00473 /**
00474   * @}
00475   */
00476 
00477 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
00478   * @{
00479   */
00480 #define DFSDM_CONTINUOUS_CONV_OFF            0x00000000U           /*!< Conversion are not continuous */
00481 #define DFSDM_CONTINUOUS_CONV_ON             0x00000001U           /*!< Conversion are continuous */
00482 /**
00483   * @}
00484   */
00485 
00486 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
00487   * @{
00488   */
00489 #define DFSDM_AWD_HIGH_THRESHOLD            0x00000000U            /*!< Analog watchdog high threshold */
00490 #define DFSDM_AWD_LOW_THRESHOLD             0x00000001U            /*!< Analog watchdog low threshold */
00491 /**
00492   * @}
00493   */
00494 
00495 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
00496 /** @defgroup DFSDM_1_CLOCKOUT_SELECTION  DFSDM1 ClockOut Selection
00497   * @{
00498   */  
00499 #define DFSDM1_CKOUT_DFSDM2_CKOUT           0x00000080U
00500 #define DFSDM1_CKOUT_DFSDM1                 0x00000000U
00501 /**
00502   * @}
00503   */  
00504   
00505 /** @defgroup DFSDM_2_CLOCKOUT_SELECTION  DFSDM2 ClockOut Selection
00506   * @{
00507   */ 
00508 #define DFSDM2_CKOUT_DFSDM2_CKOUT           0x00040000U
00509 #define DFSDM2_CKOUT_DFSDM2                 0x00000000U  
00510 /**
00511   * @}
00512   */ 
00513 
00514 /** @defgroup DFSDM_1_CLOCKIN_SELECTION  DFSDM1 ClockIn Selection
00515   * @{
00516   */ 
00517 #define DFSDM1_CKIN_DFSDM2_CKOUT            0x00000040U
00518 #define DFSDM1_CKIN_PAD                     0x00000000U
00519 /**
00520   * @}
00521   */
00522 
00523 /** @defgroup DFSDM_2_CLOCKIN_SELECTION  DFSDM2 ClockIn Selection
00524   * @{
00525   */ 
00526 #define DFSDM2_CKIN_DFSDM2_CKOUT            0x00020000U
00527 #define DFSDM2_CKIN_PAD                     0x00000000U
00528 /**
00529   * @}
00530   */
00531 
00532 /** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION  DFSDM1 Bit Stream Distribution 
00533   * @{
00534   */ 
00535 #define DFSDM1_T4_OC2_BITSTREAM_CKIN0       0x00000000U                   /* TIM4_OC2 to CLKIN0 */
00536 #define DFSDM1_T4_OC2_BITSTREAM_CKIN2       SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */
00537 #define DFSDM1_T4_OC1_BITSTREAM_CKIN3       SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */
00538 #define DFSDM1_T4_OC1_BITSTREAM_CKIN1       0x00000000U                   /* TIM4_OC1 to CLKIN1 */
00539 /**
00540   * @}
00541   */
00542   
00543 /** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION  DFSDM12 Bit Stream Distribution 
00544   * @{
00545   */
00546 #define DFSDM2_T3_OC4_BITSTREAM_CKIN0       0x00000000U                   /* TIM3_OC4 to CKIN0 */ 
00547 #define DFSDM2_T3_OC4_BITSTREAM_CKIN4       SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */ 
00548 #define DFSDM2_T3_OC3_BITSTREAM_CKIN5       SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */ 
00549 #define DFSDM2_T3_OC3_BITSTREAM_CKIN1       0x00000000U                   /* TIM3_OC3 to CKIN1 */ 
00550 #define DFSDM2_T3_OC2_BITSTREAM_CKIN6       SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */
00551 #define DFSDM2_T3_OC2_BITSTREAM_CKIN2       0x00000000U                   /* TIM3_OC2 to CKIN2 */
00552 #define DFSDM2_T3_OC1_BITSTREAM_CKIN3       0x00000000U                   /* TIM3_OC1 to CKIN3 */
00553 #define DFSDM2_T3_OC1_BITSTREAM_CKIN7       SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */
00554 /**
00555   * @}
00556   */
00557 
00558 /** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution 
00559   * @{
00560   */  
00561 #define DFSDM1_DATIN0_TO_DATIN0_PAD       0x00000000U
00562 #define DFSDM1_DATIN0_TO_DATIN1_PAD       SYSCFG_MCHDLYCR_DFSDM1D0SEL
00563 #define DFSDM1_DATIN2_TO_DATIN2_PAD       0x00000000U
00564 #define DFSDM1_DATIN2_TO_DATIN3_PAD       SYSCFG_MCHDLYCR_DFSDM1D2SEL
00565 /**
00566   * @}
00567   */
00568   
00569 /** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution 
00570   * @{
00571   */
00572 #define DFSDM2_DATIN0_TO_DATIN0_PAD       0x00000000U
00573 #define DFSDM2_DATIN0_TO_DATIN1_PAD       SYSCFG_MCHDLYCR_DFSDM2D0SEL
00574 #define DFSDM2_DATIN2_TO_DATIN2_PAD       0x00000000U
00575 #define DFSDM2_DATIN2_TO_DATIN3_PAD       SYSCFG_MCHDLYCR_DFSDM2D2SEL
00576 #define DFSDM2_DATIN4_TO_DATIN4_PAD       0x00000000U
00577 #define DFSDM2_DATIN4_TO_DATIN5_PAD       SYSCFG_MCHDLYCR_DFSDM2D4SEL 
00578 #define DFSDM2_DATIN6_TO_DATIN6_PAD       0x00000000U 
00579 #define DFSDM2_DATIN6_TO_DATIN7_PAD       SYSCFG_MCHDLYCR_DFSDM2D6SEL 
00580 /**
00581   * @}
00582   */
00583   
00584 /** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable
00585   * @{
00586   */
00587 #define HAL_MCHDLY_CLOCK_DFSDM2       SYSCFG_MCHDLYCR_MCHDLY2EN
00588 #define HAL_MCHDLY_CLOCK_DFSDM1       SYSCFG_MCHDLYCR_MCHDLY1EN
00589 /**
00590   * @}
00591   */
00592 
00593 /** @defgroup DFSDM_CLOCKIN_SOURCE  DFSDM Clock In Source Selection
00594   * @{
00595   */
00596 #define HAL_DFSDM2_CKIN_PAD           0x00040000U
00597 #define HAL_DFSDM2_CKIN_DM            SYSCFG_MCHDLYCR_DFSDM2CFG
00598 #define HAL_DFSDM1_CKIN_PAD           0x00000000U
00599 #define HAL_DFSDM1_CKIN_DM            SYSCFG_MCHDLYCR_DFSDM1CFG
00600 /**
00601   * @}
00602   */
00603   
00604 /** @defgroup DFSDM_CLOCKOUT_SOURCE   DFSDM Clock Source Selection
00605   * @{
00606   */
00607 #define HAL_DFSDM2_CKOUT_DFSDM2       0x10000000U
00608 #define HAL_DFSDM2_CKOUT_M27          SYSCFG_MCHDLYCR_DFSDM2CKOSEL
00609 #define HAL_DFSDM1_CKOUT_DFSDM1       0x00000000U
00610 #define HAL_DFSDM1_CKOUT_M27          SYSCFG_MCHDLYCR_DFSDM1CKOSEL
00611 /**
00612   * @}
00613   */
00614 
00615 /** @defgroup DFSDM_DATAIN0_SOURCE   DFSDM Source Selection For DATAIN0
00616   * @{
00617   */
00618 #define HAL_DATAIN0_DFSDM2_PAD        0x10000000U
00619 #define HAL_DATAIN0_DFSDM2_DATAIN1    SYSCFG_MCHDLYCR_DFSDM2D0SEL
00620 #define HAL_DATAIN0_DFSDM1_PAD        0x00000000U
00621 #define HAL_DATAIN0_DFSDM1_DATAIN1    SYSCFG_MCHDLYCR_DFSDM1D0SEL
00622 /**
00623   * @}
00624   */
00625 
00626 /** @defgroup DFSDM_DATAIN2_SOURCE   DFSDM Source Selection For DATAIN2
00627   * @{
00628   */
00629 #define HAL_DATAIN2_DFSDM2_PAD        0x10000000U
00630 #define HAL_DATAIN2_DFSDM2_DATAIN3    SYSCFG_MCHDLYCR_DFSDM2D2SEL
00631 #define HAL_DATAIN2_DFSDM1_PAD        0x00000000U
00632 #define HAL_DATAIN2_DFSDM1_DATAIN3    SYSCFG_MCHDLYCR_DFSDM1D2SEL
00633 /**
00634   * @}
00635   */ 
00636  
00637 /** @defgroup DFSDM_DATAIN4_SOURCE   DFSDM Source Selection For DATAIN4
00638   * @{
00639   */
00640 #define HAL_DATAIN4_DFSDM2_PAD        0x00000000U
00641 #define HAL_DATAIN4_DFSDM2_DATAIN5    SYSCFG_MCHDLYCR_DFSDM2D4SEL
00642 /**
00643   * @}
00644   */ 
00645   
00646 /** @defgroup DFSDM_DATAIN6_SOURCE   DFSDM Source Selection For DATAIN6
00647   * @{
00648   */
00649 #define HAL_DATAIN6_DFSDM2_PAD        0x00000000U
00650 #define HAL_DATAIN6_DFSDM2_DATAIN7    SYSCFG_MCHDLYCR_DFSDM2D6SEL
00651 /**
00652   * @}
00653   */ 
00654 
00655 /** @defgroup DFSDM1_CLKIN_SOURCE   DFSDM1 Source Selection For CLKIN
00656   * @{
00657   */
00658 #define HAL_DFSDM1_CLKIN0_TIM4OC2      0x01000000U
00659 #define HAL_DFSDM1_CLKIN2_TIM4OC2      SYSCFG_MCHDLYCR_DFSDM1CK02SEL
00660 #define HAL_DFSDM1_CLKIN1_TIM4OC1      0x02000000U
00661 #define HAL_DFSDM1_CLKIN3_TIM4OC1      SYSCFG_MCHDLYCR_DFSDM1CK13SEL
00662 /**
00663   * @}
00664   */ 
00665   
00666 /** @defgroup DFSDM2_CLKIN_SOURCE  DFSDM2 Source Selection For CLKIN
00667   * @{
00668   */
00669 #define HAL_DFSDM2_CLKIN0_TIM3OC4      0x04000000U
00670 #define HAL_DFSDM2_CLKIN4_TIM3OC4      SYSCFG_MCHDLYCR_DFSDM2CK04SEL
00671 #define HAL_DFSDM2_CLKIN1_TIM3OC3      0x08000000U
00672 #define HAL_DFSDM2_CLKIN5_TIM3OC3      SYSCFG_MCHDLYCR_DFSDM2CK15SEL
00673 #define HAL_DFSDM2_CLKIN2_TIM3OC2      0x10000000U
00674 #define HAL_DFSDM2_CLKIN6_TIM3OC2      SYSCFG_MCHDLYCR_DFSDM2CK26SEL
00675 #define HAL_DFSDM2_CLKIN3_TIM3OC1      0x00000000U
00676 #define HAL_DFSDM2_CLKIN7_TIM3OC1      SYSCFG_MCHDLYCR_DFSDM2CK37SEL
00677 /**
00678   * @}
00679   */    
00680        
00681 #endif /* SYSCFG_MCHDLYCR_BSCKSEL*/
00682 /**
00683   * @}
00684   */ 
00685 /* End of exported constants -------------------------------------------------*/
00686 
00687 /* Exported macros -----------------------------------------------------------*/
00688 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
00689  * @{
00690  */
00691 
00692 /** @brief  Reset DFSDM channel handle state.
00693   * @param  __HANDLE__ DFSDM channel handle.
00694   * @retval None
00695   */
00696 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
00697 
00698 /** @brief  Reset DFSDM filter handle state.
00699   * @param  __HANDLE__ DFSDM filter handle.
00700   * @retval None
00701   */
00702 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
00703 
00704 /**
00705   * @}
00706   */
00707 /* End of exported macros ----------------------------------------------------*/
00708 
00709 /* Exported functions --------------------------------------------------------*/
00710 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
00711   * @{
00712   */
00713 
00714 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
00715   * @{
00716   */
00717 /* Channel initialization and de-initialization functions *********************/
00718 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00719 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00720 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00721 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00722 /**
00723   * @}
00724   */
00725 
00726 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
00727   * @{
00728   */
00729 /* Channel operation functions ************************************************/
00730 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00731 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00732 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00733 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00734 
00735 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
00736 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
00737 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00738 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00739 
00740 int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00741 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
00742 
00743 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
00744 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
00745 
00746 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00747 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00748 /**
00749   * @}
00750   */
00751 
00752 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
00753   * @{
00754   */
00755 /* Channel state function *****************************************************/
00756 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
00757 /**
00758   * @}
00759   */
00760 
00761 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
00762   * @{
00763   */
00764 /* Filter initialization and de-initialization functions *********************/
00765 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00766 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00767 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00768 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00769 /**
00770   * @}
00771   */
00772 
00773 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
00774   * @{
00775   */
00776 /* Filter control functions *********************/
00777 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00778                                                    uint32_t                    Channel,
00779                                                    uint32_t                    ContinuousMode);
00780 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00781                                                    uint32_t                    Channel);
00782 /**
00783   * @}
00784   */
00785 
00786 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
00787   * @{
00788   */
00789 /* Filter operation functions *********************/
00790 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00791 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00792 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
00793 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
00794 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00795 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00796 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00797 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00798 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00799 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
00800 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
00801 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00802 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00803 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00804 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
00805                                               DFSDM_Filter_AwdParamTypeDef* awdParam);
00806 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00807 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
00808 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00809 
00810 int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00811 int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00812 int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00813 int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
00814 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00815 
00816 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00817 
00818 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
00819 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
00820 
00821 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00822 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00823 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00824 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00825 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
00826 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00827 /**
00828   * @}
00829   */
00830 
00831 /** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
00832   * @{
00833   */
00834 /* Filter state functions *****************************************************/
00835 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00836 uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
00837 /**
00838   * @}
00839   */
00840 /** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions
00841   * @{
00842   */
00843 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
00844 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct);
00845 void HAL_DFSDM_BitstreamClock_Start(void);
00846 void HAL_DFSDM_BitstreamClock_Stop(void);
00847 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY);
00848 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY);
00849 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source);
00850 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source);
00851 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source);
00852 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source);
00853 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source);
00854 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source);
00855 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);
00856 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
00857 /**
00858   * @}
00859   */
00860 /**
00861   * @}
00862   */
00863 /* End of exported functions -------------------------------------------------*/
00864 
00865 /* Private macros ------------------------------------------------------------*/
00866 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
00867 * @{
00868 */
00869 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
00870                                                        ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
00871 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))
00872 #define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
00873                                                        ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
00874 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
00875                                                        ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
00876                                                        ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
00877 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
00878                                                        ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
00879 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
00880                                                        ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
00881                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
00882                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
00883 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
00884                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
00885                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
00886                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
00887 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
00888                                                        ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
00889                                                        ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
00890                                                        ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
00891 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))
00892 #define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
00893 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)
00894 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)
00895 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
00896                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
00897 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
00898                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
00899                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
00900 #if defined (STM32F413xx) || defined (STM32F423xx)
00901 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
00902                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
00903                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
00904                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
00905                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \
00906                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
00907                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \
00908                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
00909                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11)    || \
00910                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
00911 #define IS_DFSDM_DELAY_CLOCK(CLOCK)                     (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \
00912                                                          ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1)) 
00913 #else
00914 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
00915                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
00916                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
00917                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
00918                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
00919                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
00920                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
00921                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
00922 #endif
00923 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
00924                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
00925                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
00926 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
00927                                                        ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
00928                                                        ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
00929                                                        ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
00930                                                        ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
00931                                                        ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
00932 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))
00933 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))
00934 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \
00935                                                        ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
00936 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
00937 #define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0x0FU)
00938 #if defined(DFSDM2_Channel0)
00939 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
00940                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \
00941                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \
00942                                                        ((CHANNEL) == DFSDM_CHANNEL_3)  || \
00943                                                        ((CHANNEL) == DFSDM_CHANNEL_4)  || \
00944                                                        ((CHANNEL) == DFSDM_CHANNEL_5)  || \
00945                                                        ((CHANNEL) == DFSDM_CHANNEL_6)  || \
00946                                                        ((CHANNEL) == DFSDM_CHANNEL_7))
00947 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
00948 #else
00949 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \
00950                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \
00951                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \
00952                                                        ((CHANNEL) == DFSDM_CHANNEL_3))
00953 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))
00954 #endif
00955 #define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
00956                                                        ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
00957 #if defined(DFSDM2_Channel0)
00958 #define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE)          (((INSTANCE) == DFSDM1_Channel0) || \
00959                                                        ((INSTANCE) == DFSDM1_Channel1) || \
00960                                                        ((INSTANCE) == DFSDM1_Channel2) || \
00961                                                        ((INSTANCE) == DFSDM1_Channel3))
00962 #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE)          (((INSTANCE) == DFSDM1_Filter0) || \
00963                                                       ((INSTANCE) == DFSDM1_Filter1)) 
00964 #endif /* DFSDM2_Channel0 */
00965 
00966 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
00967 #define IS_DFSDM_CLOCKIN_SELECTION(SELECTION)           (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \
00968                                                           ((SELECTION) == HAL_DFSDM2_CKIN_DM)  || \
00969                                                           ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \
00970                                                           ((SELECTION) == HAL_DFSDM1_CKIN_DM)) 
00971 #define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION)         (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \
00972                                                           ((SELECTION) == HAL_DFSDM2_CKOUT_M27)    || \
00973                                                           ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \
00974                                                           ((SELECTION) == HAL_DFSDM1_CKOUT_M27)) 
00975 #define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION)        (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD)    || \
00976                                                           ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \
00977                                                           ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD)     || \
00978                                                           ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1))
00979 #define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION)        (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD)    || \
00980                                                           ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \
00981                                                           ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD)     || \
00982                                                           ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3))
00983 #define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION)        (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD)    || \
00984                                                           ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5))
00985 #define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION)         (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD)    || \
00986                                                           ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7))
00987 #define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \
00988                                                           ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \
00989                                                           ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \
00990                                                           ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \
00991                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \
00992                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \
00993                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \
00994                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \
00995                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \
00996                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \
00997                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \
00998                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1))
00999 #define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT)                 (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT)    || \
01000                                                         ((CLKOUT) == DFSDM1_CKOUT_DFSDM1))
01001 #define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT)                 (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT)    || \
01002                                                         ((CLKOUT) == DFSDM2_CKOUT_DFSDM2))   
01003 #define IS_DFSDM_DFSDM1_CLKIN(CLKIN)                   (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT)    || \
01004                                                         ((CLKIN) == DFSDM1_CKIN_PAD))                                   
01005 #define IS_DFSDM_DFSDM2_CLKIN(CLKIN)                   (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT)    || \
01006                                                         ((CLKIN) == DFSDM2_CKIN_PAD))
01007 #define IS_DFSDM_DFSDM1_BIT_CLK(CLK)                   (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0)  || \
01008                                                         ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2)  || \
01009                                                         ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3)  || \
01010                                                         ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1)  || \
01011                                                         ((CLK) <= 0x30U)) 
01012 
01013 #define IS_DFSDM_DFSDM2_BIT_CLK(CLK)                   (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0)  || \
01014                                                         ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4)  || \
01015                                                         ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5)  || \
01016                                                         ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1)  || \
01017                                                         ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6)  || \
01018                                                         ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2)  || \
01019                                                         ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3)  || \
01020                                                         ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \
01021                                                         ((CLK) <= 0x1E000U)) 
01022 
01023 #define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \
01024                                                         ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \
01025                                                         ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \
01026                                                         ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \
01027                                                         ((DISTRIBUTION) <= 0xCU)) 
01028                                                       
01029 #define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \
01030                                                         ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \
01031                                                         ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \
01032                                                         ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \
01033                                                         ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \
01034                                                         ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \
01035                                                         ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \
01036                                                         ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \
01037                                                         ((DISTRIBUTION) <= 0x1D00U))                                                                                       
01038 #endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */
01039 /**
01040   * @}
01041   */ 
01042 /* End of private macros -----------------------------------------------------*/
01043 
01044 /**
01045   * @}
01046   */ 
01047 
01048 /**
01049   * @}
01050   */
01051 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
01052 #ifdef __cplusplus
01053 }
01054 #endif
01055 
01056 #endif /* __STM32F4xx_HAL_DFSDM_H */
01057 
01058 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/