STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dfsdm.c 00004 * @author MCD Application Team 00005 * @brief This file provides firmware functions to manage the following 00006 * functionalities of the Digital Filter for Sigma-Delta Modulators 00007 * (DFSDM) peripherals: 00008 * + Initialization and configuration of channels and filters 00009 * + Regular channels configuration 00010 * + Injected channels configuration 00011 * + Regular/Injected Channels DMA Configuration 00012 * + Interrupts and flags management 00013 * + Analog watchdog feature 00014 * + Short-circuit detector feature 00015 * + Extremes detector feature 00016 * + Clock absence detector feature 00017 * + Break generation on analog watchdog or short-circuit event 00018 * 00019 @verbatim 00020 ============================================================================== 00021 ##### How to use this driver ##### 00022 ============================================================================== 00023 [..] 00024 *** Channel initialization *** 00025 ============================== 00026 [..] 00027 (#) User has first to initialize channels (before filters initialization). 00028 (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() : 00029 (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE(). 00030 (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). 00031 (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init(). 00032 (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global 00033 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). 00034 (#) Configure the output clock, input, serial interface, analog watchdog, 00035 offset and data right bit shift parameters for this channel using the 00036 HAL_DFSDM_ChannelInit() function. 00037 00038 *** Channel clock absence detector *** 00039 ====================================== 00040 [..] 00041 (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or 00042 HAL_DFSDM_ChannelCkabStart_IT(). 00043 (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock 00044 absence. 00045 (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if 00046 clock absence is detected. 00047 (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or 00048 HAL_DFSDM_ChannelCkabStop_IT(). 00049 (#) Please note that the same mode (polling or interrupt) has to be used 00050 for all channels because the channels are sharing the same interrupt. 00051 (#) Please note also that in interrupt mode, if clock absence detector is 00052 stopped for one channel, interrupt will be disabled for all channels. 00053 00054 *** Channel short circuit detector *** 00055 ====================================== 00056 [..] 00057 (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or 00058 or HAL_DFSDM_ChannelScdStart_IT(). 00059 (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short 00060 circuit. 00061 (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if 00062 short circuit is detected. 00063 (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or 00064 or HAL_DFSDM_ChannelScdStop_IT(). 00065 (#) Please note that the same mode (polling or interrupt) has to be used 00066 for all channels because the channels are sharing the same interrupt. 00067 (#) Please note also that in interrupt mode, if short circuit detector is 00068 stopped for one channel, interrupt will be disabled for all channels. 00069 00070 *** Channel analog watchdog value *** 00071 ===================================== 00072 [..] 00073 (#) Get analog watchdog filter value of a channel using 00074 HAL_DFSDM_ChannelGetAwdValue(). 00075 00076 *** Channel offset value *** 00077 ===================================== 00078 [..] 00079 (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset(). 00080 00081 *** Filter initialization *** 00082 ============================= 00083 [..] 00084 (#) After channel initialization, user has to init filters. 00085 (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() : 00086 (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global 00087 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). 00088 Please note that DFSDMz_FLT0 global interrupt could be already 00089 enabled if interrupt is used for channel. 00090 (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it 00091 with DFSDMz filter handle using __HAL_LINKDMA(). 00092 (#) Configure the regular conversion, injected conversion and filter 00093 parameters for this filter using the HAL_DFSDM_FilterInit() function. 00094 00095 *** Filter regular channel conversion *** 00096 ========================================= 00097 [..] 00098 (#) Select regular channel and enable/disable continuous mode using 00099 HAL_DFSDM_FilterConfigRegChannel(). 00100 (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(), 00101 HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or 00102 HAL_DFSDM_FilterRegularMsbStart_DMA(). 00103 (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect 00104 the end of regular conversion. 00105 (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called 00106 at the end of regular conversion. 00107 (#) Get value of regular conversion and corresponding channel using 00108 HAL_DFSDM_FilterGetRegularValue(). 00109 (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and 00110 HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the 00111 half transfer and at the transfer complete. Please note that 00112 HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA 00113 circular mode. 00114 (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(), 00115 HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA(). 00116 00117 *** Filter injected channels conversion *** 00118 =========================================== 00119 [..] 00120 (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel(). 00121 (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(), 00122 HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or 00123 HAL_DFSDM_FilterInjectedMsbStart_DMA(). 00124 (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect 00125 the end of injected conversion. 00126 (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called 00127 at the end of injected conversion. 00128 (#) Get value of injected conversion and corresponding channel using 00129 HAL_DFSDM_FilterGetInjectedValue(). 00130 (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and 00131 HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the 00132 half transfer and at the transfer complete. Please note that 00133 HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA 00134 circular mode. 00135 (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(), 00136 HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA(). 00137 00138 *** Filter analog watchdog *** 00139 ============================== 00140 [..] 00141 (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT(). 00142 (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs. 00143 (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT(). 00144 00145 *** Filter extreme detector *** 00146 =============================== 00147 [..] 00148 (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart(). 00149 (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue(). 00150 (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue(). 00151 (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop(). 00152 00153 *** Filter conversion time *** 00154 ============================== 00155 [..] 00156 (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue(). 00157 00158 @endverbatim 00159 ****************************************************************************** 00160 * @attention 00161 * 00162 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00163 * 00164 * Redistribution and use in source and binary forms, with or without modification, 00165 * are permitted provided that the following conditions are met: 00166 * 1. Redistributions of source code must retain the above copyright notice, 00167 * this list of conditions and the following disclaimer. 00168 * 2. Redistributions in binary form must reproduce the above copyright notice, 00169 * this list of conditions and the following disclaimer in the documentation 00170 * and/or other materials provided with the distribution. 00171 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00172 * may be used to endorse or promote products derived from this software 00173 * without specific prior written permission. 00174 * 00175 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00176 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00177 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00178 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00179 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00180 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00181 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00182 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00183 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00184 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00185 * 00186 ****************************************************************************** 00187 */ 00188 00189 /* Includes ------------------------------------------------------------------*/ 00190 #include "stm32f4xx_hal.h" 00191 00192 /** @addtogroup STM32F4xx_HAL_Driver 00193 * @{ 00194 */ 00195 #ifdef HAL_DFSDM_MODULE_ENABLED 00196 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00197 /** @defgroup DFSDM DFSDM 00198 * @brief DFSDM HAL driver module 00199 * @{ 00200 */ 00201 00202 /* Private typedef -----------------------------------------------------------*/ 00203 /* Private define ------------------------------------------------------------*/ 00204 /** @defgroup DFSDM_Private_Define DFSDM Private Define 00205 * @{ 00206 */ 00207 00208 #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8U 00209 00210 #define DFSDM_MSB_MASK 0xFFFF0000U 00211 #define DFSDM_LSB_MASK 0x0000FFFFU 00212 #define DFSDM_CKAB_TIMEOUT 5000U 00213 #define DFSDM1_CHANNEL_NUMBER 4U 00214 #if defined (DFSDM2_Channel0) 00215 #define DFSDM2_CHANNEL_NUMBER 8U 00216 #endif /* DFSDM2_Channel0 */ 00217 00218 /** 00219 * @} 00220 */ 00221 /** @addtogroup DFSDM_Private_Macros 00222 * @{ 00223 */ 00224 00225 /** 00226 * @} 00227 */ 00228 /* Private macro -------------------------------------------------------------*/ 00229 /* Private variables ---------------------------------------------------------*/ 00230 /** @defgroup DFSDM_Private_Variables DFSDM Private Variables 00231 * @{ 00232 */ 00233 __IO uint32_t v_dfsdm1ChannelCounter = 0U; 00234 DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}; 00235 00236 #if defined (DFSDM2_Channel0) 00237 __IO uint32_t v_dfsdm2ChannelCounter = 0U; 00238 DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NULL}; 00239 #endif /* DFSDM2_Channel0 */ 00240 /** 00241 * @} 00242 */ 00243 00244 /* Private function prototypes -----------------------------------------------*/ 00245 /** @defgroup DFSDM_Private_Functions DFSDM Private Functions 00246 * @{ 00247 */ 00248 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); 00249 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance); 00250 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00251 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); 00252 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); 00253 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); 00254 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma); 00255 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma); 00256 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma); 00257 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma); 00258 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); 00259 00260 /** 00261 * @} 00262 */ 00263 00264 /* Exported functions --------------------------------------------------------*/ 00265 /** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions 00266 * @{ 00267 */ 00268 00269 /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 00270 * @brief Channel initialization and de-initialization functions 00271 * 00272 @verbatim 00273 ============================================================================== 00274 ##### Channel initialization and de-initialization functions ##### 00275 ============================================================================== 00276 [..] This section provides functions allowing to: 00277 (+) Initialize the DFSDM channel. 00278 (+) De-initialize the DFSDM channel. 00279 @endverbatim 00280 * @{ 00281 */ 00282 00283 /** 00284 * @brief Initialize the DFSDM channel according to the specified parameters 00285 * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. 00286 * @param hdfsdm_channel DFSDM channel handle. 00287 * @retval HAL status. 00288 */ 00289 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00290 { 00291 #if defined(DFSDM2_Channel0) 00292 __IO uint32_t* channelCounterPtr; 00293 DFSDM_Channel_HandleTypeDef **channelHandleTable; 00294 DFSDM_Channel_TypeDef* channel0Instance; 00295 #endif /* defined(DFSDM2_Channel0) */ 00296 00297 /* Check DFSDM Channel handle */ 00298 if(hdfsdm_channel == NULL) 00299 { 00300 return HAL_ERROR; 00301 } 00302 00303 /* Check parameters */ 00304 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 00305 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation)); 00306 assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer)); 00307 assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking)); 00308 assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins)); 00309 assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type)); 00310 assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock)); 00311 assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder)); 00312 assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling)); 00313 assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset)); 00314 assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift)); 00315 00316 #if defined(DFSDM2_Channel0) 00317 /* Get channel counter, channel handle table and channel 0 instance */ 00318 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 00319 { 00320 channelCounterPtr = &v_dfsdm1ChannelCounter; 00321 channelHandleTable = a_dfsdm1ChannelHandle; 00322 channel0Instance = DFSDM1_Channel0; 00323 } 00324 else 00325 { 00326 channelCounterPtr = &v_dfsdm2ChannelCounter; 00327 channelHandleTable = a_dfsdm2ChannelHandle; 00328 channel0Instance = DFSDM2_Channel0; 00329 } 00330 00331 /* Check that channel has not been already initialized */ 00332 if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) 00333 { 00334 return HAL_ERROR; 00335 } 00336 00337 /* Call MSP init function */ 00338 HAL_DFSDM_ChannelMspInit(hdfsdm_channel); 00339 00340 /* Update the channel counter */ 00341 (*channelCounterPtr)++; 00342 00343 /* Configure output serial clock and enable global DFSDM interface only for first channel */ 00344 if(*channelCounterPtr == 1U) 00345 { 00346 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection)); 00347 /* Set the output serial clock source */ 00348 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); 00349 channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; 00350 00351 /* Reset clock divider */ 00352 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); 00353 if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) 00354 { 00355 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); 00356 /* Set the output clock divider */ 00357 channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << 00358 DFSDM_CHCFGR1_CKOUTDIV_Pos); 00359 } 00360 00361 /* enable the DFSDM global interface */ 00362 channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; 00363 } 00364 00365 /* Set channel input parameters */ 00366 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | 00367 DFSDM_CHCFGR1_CHINSEL); 00368 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | 00369 hdfsdm_channel->Init.Input.DataPacking | 00370 hdfsdm_channel->Init.Input.Pins); 00371 00372 /* Set serial interface parameters */ 00373 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); 00374 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | 00375 hdfsdm_channel->Init.SerialInterface.SpiClock); 00376 00377 /* Set analog watchdog parameters */ 00378 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); 00379 hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | 00380 ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); 00381 00382 /* Set channel offset and right bit shift */ 00383 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); 00384 hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | 00385 (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); 00386 00387 /* Enable DFSDM channel */ 00388 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; 00389 00390 /* Set DFSDM Channel to ready state */ 00391 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; 00392 00393 /* Store channel handle in DFSDM channel handle table */ 00394 channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; 00395 00396 #else 00397 /* Check that channel has not been already initialized */ 00398 if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) 00399 { 00400 return HAL_ERROR; 00401 } 00402 00403 /* Call MSP init function */ 00404 HAL_DFSDM_ChannelMspInit(hdfsdm_channel); 00405 00406 /* Update the channel counter */ 00407 v_dfsdm1ChannelCounter++; 00408 00409 /* Configure output serial clock and enable global DFSDM interface only for first channel */ 00410 if(v_dfsdm1ChannelCounter == 1U) 00411 { 00412 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection)); 00413 /* Set the output serial clock source */ 00414 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); 00415 DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; 00416 00417 /* Reset clock divider */ 00418 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); 00419 if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) 00420 { 00421 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); 00422 /* Set the output clock divider */ 00423 DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << 00424 DFSDM_CHCFGR1_CKOUTDIV_Pos); 00425 } 00426 00427 /* enable the DFSDM global interface */ 00428 DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; 00429 } 00430 00431 /* Set channel input parameters */ 00432 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | 00433 DFSDM_CHCFGR1_CHINSEL); 00434 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | 00435 hdfsdm_channel->Init.Input.DataPacking | 00436 hdfsdm_channel->Init.Input.Pins); 00437 00438 /* Set serial interface parameters */ 00439 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); 00440 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | 00441 hdfsdm_channel->Init.SerialInterface.SpiClock); 00442 00443 /* Set analog watchdog parameters */ 00444 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); 00445 hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | 00446 ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); 00447 00448 /* Set channel offset and right bit shift */ 00449 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); 00450 hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | 00451 (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); 00452 00453 /* Enable DFSDM channel */ 00454 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; 00455 00456 /* Set DFSDM Channel to ready state */ 00457 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; 00458 00459 /* Store channel handle in DFSDM channel handle table */ 00460 a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; 00461 #endif /* DFSDM2_Channel0 */ 00462 00463 return HAL_OK; 00464 } 00465 00466 /** 00467 * @brief De-initialize the DFSDM channel. 00468 * @param hdfsdm_channel DFSDM channel handle. 00469 * @retval HAL status. 00470 */ 00471 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00472 { 00473 #if defined(DFSDM2_Channel0) 00474 __IO uint32_t* channelCounterPtr; 00475 DFSDM_Channel_HandleTypeDef **channelHandleTable; 00476 DFSDM_Channel_TypeDef* channel0Instance; 00477 #endif /* defined(DFSDM2_Channel0) */ 00478 00479 /* Check DFSDM Channel handle */ 00480 if(hdfsdm_channel == NULL) 00481 { 00482 return HAL_ERROR; 00483 } 00484 00485 /* Check parameters */ 00486 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 00487 00488 #if defined(DFSDM2_Channel0) 00489 /* Get channel counter, channel handle table and channel 0 instance */ 00490 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 00491 { 00492 channelCounterPtr = &v_dfsdm1ChannelCounter; 00493 channelHandleTable = a_dfsdm1ChannelHandle; 00494 channel0Instance = DFSDM1_Channel0; 00495 } 00496 else 00497 { 00498 channelCounterPtr = &v_dfsdm2ChannelCounter; 00499 channelHandleTable = a_dfsdm2ChannelHandle; 00500 channel0Instance = DFSDM2_Channel0; 00501 } 00502 00503 /* Check that channel has not been already deinitialized */ 00504 if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) 00505 { 00506 return HAL_ERROR; 00507 } 00508 00509 /* Disable the DFSDM channel */ 00510 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); 00511 00512 /* Update the channel counter */ 00513 (*channelCounterPtr)--; 00514 00515 /* Disable global DFSDM at deinit of last channel */ 00516 if(*channelCounterPtr == 0U) 00517 { 00518 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN); 00519 } 00520 00521 /* Call MSP deinit function */ 00522 HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel); 00523 00524 /* Set DFSDM Channel in reset state */ 00525 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET; 00526 00527 /* Reset channel handle in DFSDM channel handle table */ 00528 channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = NULL; 00529 #else 00530 /* Check that channel has not been already deinitialized */ 00531 if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) 00532 { 00533 return HAL_ERROR; 00534 } 00535 00536 /* Disable the DFSDM channel */ 00537 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); 00538 00539 /* Update the channel counter */ 00540 v_dfsdm1ChannelCounter--; 00541 00542 /* Disable global DFSDM at deinit of last channel */ 00543 if(v_dfsdm1ChannelCounter == 0U) 00544 { 00545 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN); 00546 } 00547 00548 /* Call MSP deinit function */ 00549 HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel); 00550 00551 /* Set DFSDM Channel in reset state */ 00552 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET; 00553 00554 /* Reset channel handle in DFSDM channel handle table */ 00555 a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL; 00556 #endif /* defined(DFSDM2_Channel0) */ 00557 00558 return HAL_OK; 00559 } 00560 00561 /** 00562 * @brief Initialize the DFSDM channel MSP. 00563 * @param hdfsdm_channel DFSDM channel handle. 00564 * @retval None 00565 */ 00566 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00567 { 00568 /* Prevent unused argument(s) compilation warning */ 00569 UNUSED(hdfsdm_channel); 00570 /* NOTE : This function should not be modified, when the function is needed, 00571 the HAL_DFSDM_ChannelMspInit could be implemented in the user file. 00572 */ 00573 } 00574 00575 /** 00576 * @brief De-initialize the DFSDM channel MSP. 00577 * @param hdfsdm_channel DFSDM channel handle. 00578 * @retval None 00579 */ 00580 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00581 { 00582 /* Prevent unused argument(s) compilation warning */ 00583 UNUSED(hdfsdm_channel); 00584 /* NOTE : This function should not be modified, when the function is needed, 00585 the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file. 00586 */ 00587 } 00588 00589 /** 00590 * @} 00591 */ 00592 00593 /** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 00594 * @brief Channel operation functions 00595 * 00596 @verbatim 00597 ============================================================================== 00598 ##### Channel operation functions ##### 00599 ============================================================================== 00600 [..] This section provides functions allowing to: 00601 (+) Manage clock absence detector feature. 00602 (+) Manage short circuit detector feature. 00603 (+) Get analog watchdog value. 00604 (+) Modify offset value. 00605 @endverbatim 00606 * @{ 00607 */ 00608 00609 /** 00610 * @brief This function allows to start clock absence detection in polling mode. 00611 * @note Same mode has to be used for all channels. 00612 * @note If clock is not available on this channel during 5 seconds, 00613 * clock absence detection will not be activated and function 00614 * will return HAL_TIMEOUT error. 00615 * @param hdfsdm_channel DFSDM channel handle. 00616 * @retval HAL status 00617 */ 00618 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00619 { 00620 HAL_StatusTypeDef status = HAL_OK; 00621 uint32_t tickstart; 00622 uint32_t channel; 00623 00624 #if defined(DFSDM2_Channel0) 00625 DFSDM_Filter_TypeDef* filter0Instance; 00626 #endif /* defined(DFSDM2_Channel0) */ 00627 00628 /* Check parameters */ 00629 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 00630 00631 /* Check DFSDM channel state */ 00632 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 00633 { 00634 /* Return error status */ 00635 status = HAL_ERROR; 00636 } 00637 else 00638 { 00639 #if defined (DFSDM2_Channel0) 00640 /* Get channel counter, channel handle table and channel 0 instance */ 00641 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 00642 { 00643 filter0Instance = DFSDM1_Filter0; 00644 } 00645 else 00646 { 00647 filter0Instance = DFSDM2_Filter0; 00648 } 00649 /* Get channel number from channel instance */ 00650 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 00651 00652 /* Get timeout */ 00653 tickstart = HAL_GetTick(); 00654 00655 /* Clear clock absence flag */ 00656 while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) 00657 { 00658 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 00659 00660 /* Check the Timeout */ 00661 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) 00662 { 00663 /* Set timeout status */ 00664 status = HAL_TIMEOUT; 00665 break; 00666 } 00667 } 00668 #else 00669 /* Get channel number from channel instance */ 00670 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 00671 00672 /* Get timeout */ 00673 tickstart = HAL_GetTick(); 00674 00675 /* Clear clock absence flag */ 00676 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) 00677 { 00678 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 00679 00680 /* Check the Timeout */ 00681 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) 00682 { 00683 /* Set timeout status */ 00684 status = HAL_TIMEOUT; 00685 break; 00686 } 00687 } 00688 #endif /* DFSDM2_Channel0 */ 00689 00690 if(status == HAL_OK) 00691 { 00692 /* Start clock absence detection */ 00693 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; 00694 } 00695 } 00696 /* Return function status */ 00697 return status; 00698 } 00699 00700 /** 00701 * @brief This function allows to poll for the clock absence detection. 00702 * @param hdfsdm_channel DFSDM channel handle. 00703 * @param Timeout Timeout value in milliseconds. 00704 * @retval HAL status 00705 */ 00706 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 00707 uint32_t Timeout) 00708 { 00709 uint32_t tickstart; 00710 uint32_t channel; 00711 #if defined(DFSDM2_Channel0) 00712 DFSDM_Filter_TypeDef* filter0Instance; 00713 #endif /* defined(DFSDM2_Channel0) */ 00714 00715 /* Check parameters */ 00716 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 00717 00718 /* Check DFSDM channel state */ 00719 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 00720 { 00721 /* Return error status */ 00722 return HAL_ERROR; 00723 } 00724 else 00725 { 00726 #if defined(DFSDM2_Channel0) 00727 00728 /* Get channel counter, channel handle table and channel 0 instance */ 00729 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 00730 { 00731 filter0Instance = DFSDM1_Filter0; 00732 } 00733 else 00734 { 00735 filter0Instance = DFSDM2_Filter0; 00736 } 00737 00738 /* Get channel number from channel instance */ 00739 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 00740 00741 /* Get timeout */ 00742 tickstart = HAL_GetTick(); 00743 00744 /* Wait clock absence detection */ 00745 while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U) 00746 { 00747 /* Check the Timeout */ 00748 if(Timeout != HAL_MAX_DELAY) 00749 { 00750 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 00751 { 00752 /* Return timeout status */ 00753 return HAL_TIMEOUT; 00754 } 00755 } 00756 } 00757 00758 /* Clear clock absence detection flag */ 00759 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 00760 #else 00761 /* Get channel number from channel instance */ 00762 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 00763 00764 /* Get timeout */ 00765 tickstart = HAL_GetTick(); 00766 00767 /* Wait clock absence detection */ 00768 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U) 00769 { 00770 /* Check the Timeout */ 00771 if(Timeout != HAL_MAX_DELAY) 00772 { 00773 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 00774 { 00775 /* Return timeout status */ 00776 return HAL_TIMEOUT; 00777 } 00778 } 00779 } 00780 00781 /* Clear clock absence detection flag */ 00782 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 00783 #endif /* defined(DFSDM2_Channel0) */ 00784 /* Return function status */ 00785 return HAL_OK; 00786 } 00787 } 00788 00789 /** 00790 * @brief This function allows to stop clock absence detection in polling mode. 00791 * @param hdfsdm_channel DFSDM channel handle. 00792 * @retval HAL status 00793 */ 00794 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00795 { 00796 HAL_StatusTypeDef status = HAL_OK; 00797 uint32_t channel; 00798 #if defined(DFSDM2_Channel0) 00799 DFSDM_Filter_TypeDef* filter0Instance; 00800 #endif /* defined(DFSDM2_Channel0) */ 00801 00802 /* Check parameters */ 00803 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 00804 00805 /* Check DFSDM channel state */ 00806 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 00807 { 00808 /* Return error status */ 00809 status = HAL_ERROR; 00810 } 00811 else 00812 { 00813 #if defined(DFSDM2_Channel0) 00814 00815 /* Get channel counter, channel handle table and channel 0 instance */ 00816 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 00817 { 00818 filter0Instance = DFSDM1_Filter0; 00819 } 00820 else 00821 { 00822 filter0Instance = DFSDM2_Filter0; 00823 } 00824 00825 /* Stop clock absence detection */ 00826 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); 00827 00828 /* Clear clock absence flag */ 00829 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 00830 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 00831 00832 #else 00833 /* Stop clock absence detection */ 00834 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); 00835 00836 /* Clear clock absence flag */ 00837 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 00838 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 00839 #endif /* DFSDM2_Channel0 */ 00840 } 00841 /* Return function status */ 00842 return status; 00843 } 00844 00845 /** 00846 * @brief This function allows to start clock absence detection in interrupt mode. 00847 * @note Same mode has to be used for all channels. 00848 * @note If clock is not available on this channel during 5 seconds, 00849 * clock absence detection will not be activated and function 00850 * will return HAL_TIMEOUT error. 00851 * @param hdfsdm_channel DFSDM channel handle. 00852 * @retval HAL status 00853 */ 00854 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00855 { 00856 HAL_StatusTypeDef status = HAL_OK; 00857 uint32_t channel; 00858 uint32_t tickstart; 00859 #if defined(DFSDM2_Channel0) 00860 DFSDM_Filter_TypeDef* filter0Instance; 00861 #endif /* defined(DFSDM2_Channel0) */ 00862 00863 /* Check parameters */ 00864 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 00865 00866 /* Check DFSDM channel state */ 00867 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 00868 { 00869 /* Return error status */ 00870 status = HAL_ERROR; 00871 } 00872 else 00873 { 00874 #if defined(DFSDM2_Channel0) 00875 00876 /* Get channel counter, channel handle table and channel 0 instance */ 00877 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 00878 { 00879 filter0Instance = DFSDM1_Filter0; 00880 } 00881 else 00882 { 00883 filter0Instance = DFSDM2_Filter0; 00884 } 00885 00886 /* Get channel number from channel instance */ 00887 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 00888 00889 /* Get timeout */ 00890 tickstart = HAL_GetTick(); 00891 00892 /* Clear clock absence flag */ 00893 while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) 00894 { 00895 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 00896 00897 /* Check the Timeout */ 00898 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) 00899 { 00900 /* Set timeout status */ 00901 status = HAL_TIMEOUT; 00902 break; 00903 } 00904 } 00905 00906 if(status == HAL_OK) 00907 { 00908 /* Activate clock absence detection interrupt */ 00909 filter0Instance->FLTCR2 |= DFSDM_FLTCR2_CKABIE; 00910 00911 /* Start clock absence detection */ 00912 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; 00913 } 00914 #else 00915 /* Get channel number from channel instance */ 00916 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 00917 00918 /* Get timeout */ 00919 tickstart = HAL_GetTick(); 00920 00921 /* Clear clock absence flag */ 00922 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U) 00923 { 00924 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 00925 00926 /* Check the Timeout */ 00927 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) 00928 { 00929 /* Set timeout status */ 00930 status = HAL_TIMEOUT; 00931 break; 00932 } 00933 } 00934 00935 if(status == HAL_OK) 00936 { 00937 /* Activate clock absence detection interrupt */ 00938 DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE; 00939 00940 /* Start clock absence detection */ 00941 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; 00942 } 00943 00944 #endif /* defined(DFSDM2_Channel0) */ 00945 } 00946 /* Return function status */ 00947 return status; 00948 } 00949 00950 /** 00951 * @brief Clock absence detection callback. 00952 * @param hdfsdm_channel DFSDM channel handle. 00953 * @retval None 00954 */ 00955 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00956 { 00957 /* Prevent unused argument(s) compilation warning */ 00958 UNUSED(hdfsdm_channel); 00959 /* NOTE : This function should not be modified, when the callback is needed, 00960 the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file 00961 */ 00962 } 00963 00964 /** 00965 * @brief This function allows to stop clock absence detection in interrupt mode. 00966 * @note Interrupt will be disabled for all channels 00967 * @param hdfsdm_channel DFSDM channel handle. 00968 * @retval HAL status 00969 */ 00970 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 00971 { 00972 HAL_StatusTypeDef status = HAL_OK; 00973 uint32_t channel; 00974 #if defined(DFSDM2_Channel0) 00975 DFSDM_Filter_TypeDef* filter0Instance; 00976 #endif /* defined(DFSDM2_Channel0) */ 00977 00978 /* Check parameters */ 00979 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 00980 00981 /* Check DFSDM channel state */ 00982 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 00983 { 00984 /* Return error status */ 00985 status = HAL_ERROR; 00986 } 00987 else 00988 { 00989 #if defined(DFSDM2_Channel0) 00990 00991 /* Get channel counter, channel handle table and channel 0 instance */ 00992 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 00993 { 00994 filter0Instance = DFSDM1_Filter0; 00995 } 00996 else 00997 { 00998 filter0Instance = DFSDM2_Filter0; 00999 } 01000 01001 /* Stop clock absence detection */ 01002 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); 01003 01004 /* Clear clock absence flag */ 01005 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 01006 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 01007 01008 /* Disable clock absence detection interrupt */ 01009 filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); 01010 #else 01011 01012 /* Stop clock absence detection */ 01013 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); 01014 01015 /* Clear clock absence flag */ 01016 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 01017 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 01018 01019 /* Disable clock absence detection interrupt */ 01020 DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); 01021 #endif /* DFSDM2_Channel0 */ 01022 } 01023 01024 /* Return function status */ 01025 return status; 01026 } 01027 01028 /** 01029 * @brief This function allows to start short circuit detection in polling mode. 01030 * @note Same mode has to be used for all channels 01031 * @param hdfsdm_channel DFSDM channel handle. 01032 * @param Threshold Short circuit detector threshold. 01033 * This parameter must be a number between Min_Data = 0 and Max_Data = 255. 01034 * @param BreakSignal Break signals assigned to short circuit event. 01035 * This parameter can be a values combination of @ref DFSDM_BreakSignals. 01036 * @retval HAL status 01037 */ 01038 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 01039 uint32_t Threshold, 01040 uint32_t BreakSignal) 01041 { 01042 HAL_StatusTypeDef status = HAL_OK; 01043 01044 /* Check parameters */ 01045 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 01046 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); 01047 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); 01048 01049 /* Check DFSDM channel state */ 01050 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 01051 { 01052 /* Return error status */ 01053 status = HAL_ERROR; 01054 } 01055 else 01056 { 01057 /* Configure threshold and break signals */ 01058 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); 01059 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ 01060 Threshold); 01061 01062 /* Start short circuit detection */ 01063 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; 01064 } 01065 /* Return function status */ 01066 return status; 01067 } 01068 01069 /** 01070 * @brief This function allows to poll for the short circuit detection. 01071 * @param hdfsdm_channel DFSDM channel handle. 01072 * @param Timeout Timeout value in milliseconds. 01073 * @retval HAL status 01074 */ 01075 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 01076 uint32_t Timeout) 01077 { 01078 uint32_t tickstart; 01079 uint32_t channel; 01080 #if defined(DFSDM2_Channel0) 01081 DFSDM_Filter_TypeDef* filter0Instance; 01082 #endif /* defined(DFSDM2_Channel0) */ 01083 01084 /* Check parameters */ 01085 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 01086 01087 /* Check DFSDM channel state */ 01088 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 01089 { 01090 /* Return error status */ 01091 return HAL_ERROR; 01092 } 01093 else 01094 { 01095 /* Get channel number from channel instance */ 01096 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 01097 01098 #if defined(DFSDM2_Channel0) 01099 /* Get channel counter, channel handle table and channel 0 instance */ 01100 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 01101 { 01102 filter0Instance = DFSDM1_Filter0; 01103 } 01104 else 01105 { 01106 filter0Instance = DFSDM2_Filter0; 01107 } 01108 01109 /* Get timeout */ 01110 tickstart = HAL_GetTick(); 01111 01112 /* Wait short circuit detection */ 01113 while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U) 01114 { 01115 /* Check the Timeout */ 01116 if(Timeout != HAL_MAX_DELAY) 01117 { 01118 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 01119 { 01120 /* Return timeout status */ 01121 return HAL_TIMEOUT; 01122 } 01123 } 01124 } 01125 01126 /* Clear short circuit detection flag */ 01127 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); 01128 01129 #else 01130 /* Get timeout */ 01131 tickstart = HAL_GetTick(); 01132 01133 /* Wait short circuit detection */ 01134 while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U) 01135 { 01136 /* Check the Timeout */ 01137 if(Timeout != HAL_MAX_DELAY) 01138 { 01139 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 01140 { 01141 /* Return timeout status */ 01142 return HAL_TIMEOUT; 01143 } 01144 } 01145 } 01146 01147 /* Clear short circuit detection flag */ 01148 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); 01149 #endif /* DFSDM2_Channel0 */ 01150 01151 /* Return function status */ 01152 return HAL_OK; 01153 } 01154 } 01155 01156 /** 01157 * @brief This function allows to stop short circuit detection in polling mode. 01158 * @param hdfsdm_channel DFSDM channel handle. 01159 * @retval HAL status 01160 */ 01161 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 01162 { 01163 HAL_StatusTypeDef status = HAL_OK; 01164 uint32_t channel; 01165 #if defined(DFSDM2_Channel0) 01166 DFSDM_Filter_TypeDef* filter0Instance; 01167 #endif /* defined(DFSDM2_Channel0) */ 01168 01169 /* Check parameters */ 01170 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 01171 01172 /* Check DFSDM channel state */ 01173 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 01174 { 01175 /* Return error status */ 01176 status = HAL_ERROR; 01177 } 01178 else 01179 { 01180 /* Stop short circuit detection */ 01181 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); 01182 01183 /* Clear short circuit detection flag */ 01184 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 01185 01186 #if defined(DFSDM2_Channel0) 01187 /* Get channel counter, channel handle table and channel 0 instance */ 01188 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 01189 { 01190 filter0Instance = DFSDM1_Filter0; 01191 } 01192 else 01193 { 01194 filter0Instance = DFSDM2_Filter0; 01195 } 01196 01197 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); 01198 #else 01199 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); 01200 #endif /* DFSDM2_Channel0*/ 01201 } 01202 /* Return function status */ 01203 return status; 01204 } 01205 01206 /** 01207 * @brief This function allows to start short circuit detection in interrupt mode. 01208 * @note Same mode has to be used for all channels 01209 * @param hdfsdm_channel DFSDM channel handle. 01210 * @param Threshold Short circuit detector threshold. 01211 * This parameter must be a number between Min_Data = 0 and Max_Data = 255. 01212 * @param BreakSignal Break signals assigned to short circuit event. 01213 * This parameter can be a values combination of @ref DFSDM_BreakSignals. 01214 * @retval HAL status 01215 */ 01216 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 01217 uint32_t Threshold, 01218 uint32_t BreakSignal) 01219 { 01220 HAL_StatusTypeDef status = HAL_OK; 01221 #if defined(DFSDM2_Channel0) 01222 DFSDM_Filter_TypeDef* filter0Instance; 01223 #endif /* defined(DFSDM2_Channel0) */ 01224 01225 /* Check parameters */ 01226 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 01227 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); 01228 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); 01229 01230 /* Check DFSDM channel state */ 01231 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 01232 { 01233 /* Return error status */ 01234 status = HAL_ERROR; 01235 } 01236 else 01237 { 01238 #if defined(DFSDM2_Channel0) 01239 /* Get channel counter, channel handle table and channel 0 instance */ 01240 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 01241 { 01242 filter0Instance = DFSDM1_Filter0; 01243 } 01244 else 01245 { 01246 filter0Instance = DFSDM2_Filter0; 01247 } 01248 /* Activate short circuit detection interrupt */ 01249 filter0Instance->FLTCR2 |= DFSDM_FLTCR2_SCDIE; 01250 #else 01251 /* Activate short circuit detection interrupt */ 01252 DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE; 01253 #endif /* DFSDM2_Channel0 */ 01254 01255 /* Configure threshold and break signals */ 01256 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); 01257 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ 01258 Threshold); 01259 01260 /* Start short circuit detection */ 01261 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; 01262 } 01263 /* Return function status */ 01264 return status; 01265 } 01266 01267 /** 01268 * @brief Short circuit detection callback. 01269 * @param hdfsdm_channel DFSDM channel handle. 01270 * @retval None 01271 */ 01272 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 01273 { 01274 /* Prevent unused argument(s) compilation warning */ 01275 UNUSED(hdfsdm_channel); 01276 /* NOTE : This function should not be modified, when the callback is needed, 01277 the HAL_DFSDM_ChannelScdCallback could be implemented in the user file 01278 */ 01279 } 01280 01281 /** 01282 * @brief This function allows to stop short circuit detection in interrupt mode. 01283 * @note Interrupt will be disabled for all channels 01284 * @param hdfsdm_channel DFSDM channel handle. 01285 * @retval HAL status 01286 */ 01287 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 01288 { 01289 HAL_StatusTypeDef status = HAL_OK; 01290 uint32_t channel; 01291 #if defined(DFSDM2_Channel0) 01292 DFSDM_Filter_TypeDef* filter0Instance; 01293 #endif /* defined(DFSDM2_Channel0) */ 01294 01295 /* Check parameters */ 01296 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 01297 01298 /* Check DFSDM channel state */ 01299 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 01300 { 01301 /* Return error status */ 01302 status = HAL_ERROR; 01303 } 01304 else 01305 { 01306 /* Stop short circuit detection */ 01307 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); 01308 01309 /* Clear short circuit detection flag */ 01310 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); 01311 #if defined(DFSDM2_Channel0) 01312 /* Get channel counter, channel handle table and channel 0 instance */ 01313 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) 01314 { 01315 filter0Instance = DFSDM1_Filter0; 01316 } 01317 else 01318 { 01319 filter0Instance = DFSDM2_Filter0; 01320 } 01321 01322 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); 01323 01324 /* Disable short circuit detection interrupt */ 01325 filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); 01326 #else 01327 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); 01328 01329 /* Disable short circuit detection interrupt */ 01330 DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); 01331 #endif /* DFSDM2_Channel0 */ 01332 } 01333 /* Return function status */ 01334 return status; 01335 } 01336 01337 /** 01338 * @brief This function allows to get channel analog watchdog value. 01339 * @param hdfsdm_channel DFSDM channel handle. 01340 * @retval Channel analog watchdog value. 01341 */ 01342 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 01343 { 01344 return (int16_t) hdfsdm_channel->Instance->CHWDATAR; 01345 } 01346 01347 /** 01348 * @brief This function allows to modify channel offset value. 01349 * @param hdfsdm_channel DFSDM channel handle. 01350 * @param Offset DFSDM channel offset. 01351 * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. 01352 * @retval HAL status. 01353 */ 01354 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 01355 int32_t Offset) 01356 { 01357 HAL_StatusTypeDef status = HAL_OK; 01358 01359 /* Check parameters */ 01360 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); 01361 assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset)); 01362 01363 /* Check DFSDM channel state */ 01364 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) 01365 { 01366 /* Return error status */ 01367 status = HAL_ERROR; 01368 } 01369 else 01370 { 01371 /* Modify channel offset */ 01372 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET); 01373 hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos); 01374 } 01375 /* Return function status */ 01376 return status; 01377 } 01378 01379 /** 01380 * @} 01381 */ 01382 01383 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 01384 * @brief Channel state function 01385 * 01386 @verbatim 01387 ============================================================================== 01388 ##### Channel state function ##### 01389 ============================================================================== 01390 [..] This section provides function allowing to: 01391 (+) Get channel handle state. 01392 @endverbatim 01393 * @{ 01394 */ 01395 01396 /** 01397 * @brief This function allows to get the current DFSDM channel handle state. 01398 * @param hdfsdm_channel DFSDM channel handle. 01399 * @retval DFSDM channel state. 01400 */ 01401 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) 01402 { 01403 /* Return DFSDM channel handle state */ 01404 return hdfsdm_channel->State; 01405 } 01406 01407 /** 01408 * @} 01409 */ 01410 01411 /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 01412 * @brief Filter initialization and de-initialization functions 01413 * 01414 @verbatim 01415 ============================================================================== 01416 ##### Filter initialization and de-initialization functions ##### 01417 ============================================================================== 01418 [..] This section provides functions allowing to: 01419 (+) Initialize the DFSDM filter. 01420 (+) De-initialize the DFSDM filter. 01421 @endverbatim 01422 * @{ 01423 */ 01424 01425 /** 01426 * @brief Initialize the DFSDM filter according to the specified parameters 01427 * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle. 01428 * @param hdfsdm_filter DFSDM filter handle. 01429 * @retval HAL status. 01430 */ 01431 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 01432 { 01433 /* Check DFSDM Channel handle */ 01434 if(hdfsdm_filter == NULL) 01435 { 01436 return HAL_ERROR; 01437 } 01438 01439 /* Check parameters */ 01440 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01441 assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger)); 01442 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode)); 01443 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode)); 01444 assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger)); 01445 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode)); 01446 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode)); 01447 assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder)); 01448 assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling)); 01449 assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling)); 01450 01451 /* Check parameters compatibility */ 01452 if((hdfsdm_filter->Instance == DFSDM1_Filter0) && 01453 ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || 01454 (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) 01455 { 01456 return HAL_ERROR; 01457 } 01458 #if defined (DFSDM2_Channel0) 01459 if((hdfsdm_filter->Instance == DFSDM2_Filter0) && 01460 ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || 01461 (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) 01462 { 01463 return HAL_ERROR; 01464 } 01465 #endif /* DFSDM2_Channel0 */ 01466 01467 /* Initialize DFSDM filter variables with default values */ 01468 hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF; 01469 hdfsdm_filter->InjectedChannelsNbr = 1U; 01470 hdfsdm_filter->InjConvRemaining = 1U; 01471 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE; 01472 01473 /* Call MSP init function */ 01474 HAL_DFSDM_FilterMspInit(hdfsdm_filter); 01475 01476 /* Set regular parameters */ 01477 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); 01478 if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) 01479 { 01480 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST; 01481 } 01482 else 01483 { 01484 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST); 01485 } 01486 01487 if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) 01488 { 01489 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN; 01490 } 01491 else 01492 { 01493 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN); 01494 } 01495 01496 /* Set injected parameters */ 01497 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL); 01498 if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) 01499 { 01500 assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger)); 01501 assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge)); 01502 hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger); 01503 } 01504 01505 if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) 01506 { 01507 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN; 01508 } 01509 else 01510 { 01511 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN); 01512 } 01513 01514 if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) 01515 { 01516 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN; 01517 } 01518 else 01519 { 01520 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN); 01521 } 01522 01523 /* Set filter parameters */ 01524 hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); 01525 hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | 01526 ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) | 01527 (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U)); 01528 01529 /* Store regular and injected triggers and injected scan mode*/ 01530 hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger; 01531 hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger; 01532 hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge; 01533 hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode; 01534 01535 /* Enable DFSDM filter */ 01536 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; 01537 01538 /* Set DFSDM filter to ready state */ 01539 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY; 01540 01541 return HAL_OK; 01542 } 01543 01544 /** 01545 * @brief De-initializes the DFSDM filter. 01546 * @param hdfsdm_filter DFSDM filter handle. 01547 * @retval HAL status. 01548 */ 01549 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 01550 { 01551 /* Check DFSDM filter handle */ 01552 if(hdfsdm_filter == NULL) 01553 { 01554 return HAL_ERROR; 01555 } 01556 01557 /* Check parameters */ 01558 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01559 01560 /* Disable the DFSDM filter */ 01561 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); 01562 01563 /* Call MSP deinit function */ 01564 HAL_DFSDM_FilterMspDeInit(hdfsdm_filter); 01565 01566 /* Set DFSDM filter in reset state */ 01567 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET; 01568 01569 return HAL_OK; 01570 } 01571 01572 /** 01573 * @brief Initializes the DFSDM filter MSP. 01574 * @param hdfsdm_filter DFSDM filter handle. 01575 * @retval None 01576 */ 01577 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 01578 { 01579 /* Prevent unused argument(s) compilation warning */ 01580 UNUSED(hdfsdm_filter); 01581 /* NOTE : This function should not be modified, when the function is needed, 01582 the HAL_DFSDM_FilterMspInit could be implemented in the user file. 01583 */ 01584 } 01585 01586 /** 01587 * @brief De-initializes the DFSDM filter MSP. 01588 * @param hdfsdm_filter DFSDM filter handle. 01589 * @retval None 01590 */ 01591 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 01592 { 01593 /* Prevent unused argument(s) compilation warning */ 01594 UNUSED(hdfsdm_filter); 01595 /* NOTE : This function should not be modified, when the function is needed, 01596 the HAL_DFSDM_FilterMspDeInit could be implemented in the user file. 01597 */ 01598 } 01599 01600 /** 01601 * @} 01602 */ 01603 01604 /** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 01605 * @brief Filter control functions 01606 * 01607 @verbatim 01608 ============================================================================== 01609 ##### Filter control functions ##### 01610 ============================================================================== 01611 [..] This section provides functions allowing to: 01612 (+) Select channel and enable/disable continuous mode for regular conversion. 01613 (+) Select channels for injected conversion. 01614 @endverbatim 01615 * @{ 01616 */ 01617 01618 /** 01619 * @brief This function allows to select channel and to enable/disable 01620 * continuous mode for regular conversion. 01621 * @param hdfsdm_filter DFSDM filter handle. 01622 * @param Channel Channel for regular conversion. 01623 * This parameter can be a value of @ref DFSDM_Channel_Selection. 01624 * @param ContinuousMode Enable/disable continuous mode for regular conversion. 01625 * This parameter can be a value of @ref DFSDM_ContinuousMode. 01626 * @retval HAL status 01627 */ 01628 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 01629 uint32_t Channel, 01630 uint32_t ContinuousMode) 01631 { 01632 HAL_StatusTypeDef status = HAL_OK; 01633 01634 /* Check parameters */ 01635 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01636 assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel)); 01637 assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode)); 01638 01639 /* Check DFSDM filter state */ 01640 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && 01641 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) 01642 { 01643 /* Configure channel and continuous mode for regular conversion */ 01644 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT); 01645 if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) 01646 { 01647 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) | 01648 DFSDM_FLTCR1_RCONT); 01649 } 01650 else 01651 { 01652 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET); 01653 } 01654 /* Store continuous mode information */ 01655 hdfsdm_filter->RegularContMode = ContinuousMode; 01656 } 01657 else 01658 { 01659 status = HAL_ERROR; 01660 } 01661 01662 /* Return function status */ 01663 return status; 01664 } 01665 01666 /** 01667 * @brief This function allows to select channels for injected conversion. 01668 * @param hdfsdm_filter DFSDM filter handle. 01669 * @param Channel Channels for injected conversion. 01670 * This parameter can be a values combination of @ref DFSDM_Channel_Selection. 01671 * @retval HAL status 01672 */ 01673 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 01674 uint32_t Channel) 01675 { 01676 HAL_StatusTypeDef status = HAL_OK; 01677 01678 /* Check parameters */ 01679 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01680 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); 01681 01682 /* Check DFSDM filter state */ 01683 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && 01684 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) 01685 { 01686 /* Configure channel for injected conversion */ 01687 hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK); 01688 /* Store number of injected channels */ 01689 hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel); 01690 /* Update number of injected channels remaining */ 01691 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ 01692 hdfsdm_filter->InjectedChannelsNbr : 1U; 01693 } 01694 else 01695 { 01696 status = HAL_ERROR; 01697 } 01698 /* Return function status */ 01699 return status; 01700 } 01701 01702 /** 01703 * @} 01704 */ 01705 01706 /** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 01707 * @brief Filter operation functions 01708 * 01709 @verbatim 01710 ============================================================================== 01711 ##### Filter operation functions ##### 01712 ============================================================================== 01713 [..] This section provides functions allowing to: 01714 (+) Start conversion of regular/injected channel. 01715 (+) Poll for the end of regular/injected conversion. 01716 (+) Stop conversion of regular/injected channel. 01717 (+) Start conversion of regular/injected channel and enable interrupt. 01718 (+) Call the callback functions at the end of regular/injected conversions. 01719 (+) Stop conversion of regular/injected channel and disable interrupt. 01720 (+) Start conversion of regular/injected channel and enable DMA transfer. 01721 (+) Stop conversion of regular/injected channel and disable DMA transfer. 01722 (+) Start analog watchdog and enable interrupt. 01723 (+) Call the callback function when analog watchdog occurs. 01724 (+) Stop analog watchdog and disable interrupt. 01725 (+) Start extreme detector. 01726 (+) Stop extreme detector. 01727 (+) Get result of regular channel conversion. 01728 (+) Get result of injected channel conversion. 01729 (+) Get extreme detector maximum and minimum values. 01730 (+) Get conversion time. 01731 (+) Handle DFSDM interrupt request. 01732 @endverbatim 01733 * @{ 01734 */ 01735 01736 /** 01737 * @brief This function allows to start regular conversion in polling mode. 01738 * @note This function should be called only when DFSDM filter instance is 01739 * in idle state or if injected conversion is ongoing. 01740 * @param hdfsdm_filter DFSDM filter handle. 01741 * @retval HAL status 01742 */ 01743 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 01744 { 01745 HAL_StatusTypeDef status = HAL_OK; 01746 01747 /* Check parameters */ 01748 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01749 01750 /* Check DFSDM filter state */ 01751 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ 01752 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) 01753 { 01754 /* Start regular conversion */ 01755 DFSDM_RegConvStart(hdfsdm_filter); 01756 } 01757 else 01758 { 01759 status = HAL_ERROR; 01760 } 01761 /* Return function status */ 01762 return status; 01763 } 01764 01765 /** 01766 * @brief This function allows to poll for the end of regular conversion. 01767 * @note This function should be called only if regular conversion is ongoing. 01768 * @param hdfsdm_filter DFSDM filter handle. 01769 * @param Timeout Timeout value in milliseconds. 01770 * @retval HAL status 01771 */ 01772 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 01773 uint32_t Timeout) 01774 { 01775 uint32_t tickstart; 01776 01777 /* Check parameters */ 01778 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01779 01780 /* Check DFSDM filter state */ 01781 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ 01782 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) 01783 { 01784 /* Return error status */ 01785 return HAL_ERROR; 01786 } 01787 else 01788 { 01789 /* Get timeout */ 01790 tickstart = HAL_GetTick(); 01791 01792 /* Wait end of regular conversion */ 01793 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) 01794 { 01795 /* Check the Timeout */ 01796 if(Timeout != HAL_MAX_DELAY) 01797 { 01798 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 01799 { 01800 /* Return timeout status */ 01801 return HAL_TIMEOUT; 01802 } 01803 } 01804 } 01805 /* Check if overrun occurs */ 01806 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) 01807 { 01808 /* Update error code and call error callback */ 01809 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; 01810 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); 01811 01812 /* Clear regular overrun flag */ 01813 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; 01814 } 01815 /* Update DFSDM filter state only if not continuous conversion and SW trigger */ 01816 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ 01817 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) 01818 { 01819 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ 01820 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; 01821 } 01822 /* Return function status */ 01823 return HAL_OK; 01824 } 01825 } 01826 01827 /** 01828 * @brief This function allows to stop regular conversion in polling mode. 01829 * @note This function should be called only if regular conversion is ongoing. 01830 * @param hdfsdm_filter DFSDM filter handle. 01831 * @retval HAL status 01832 */ 01833 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 01834 { 01835 HAL_StatusTypeDef status = HAL_OK; 01836 01837 /* Check parameters */ 01838 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01839 01840 /* Check DFSDM filter state */ 01841 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ 01842 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) 01843 { 01844 /* Return error status */ 01845 status = HAL_ERROR; 01846 } 01847 else 01848 { 01849 /* Stop regular conversion */ 01850 DFSDM_RegConvStop(hdfsdm_filter); 01851 } 01852 /* Return function status */ 01853 return status; 01854 } 01855 01856 /** 01857 * @brief This function allows to start regular conversion in interrupt mode. 01858 * @note This function should be called only when DFSDM filter instance is 01859 * in idle state or if injected conversion is ongoing. 01860 * @param hdfsdm_filter DFSDM filter handle. 01861 * @retval HAL status 01862 */ 01863 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 01864 { 01865 HAL_StatusTypeDef status = HAL_OK; 01866 01867 /* Check parameters */ 01868 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01869 01870 /* Check DFSDM filter state */ 01871 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ 01872 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) 01873 { 01874 /* Enable interrupts for regular conversions */ 01875 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); 01876 01877 /* Start regular conversion */ 01878 DFSDM_RegConvStart(hdfsdm_filter); 01879 } 01880 else 01881 { 01882 status = HAL_ERROR; 01883 } 01884 /* Return function status */ 01885 return status; 01886 } 01887 01888 /** 01889 * @brief This function allows to stop regular conversion in interrupt mode. 01890 * @note This function should be called only if regular conversion is ongoing. 01891 * @param hdfsdm_filter DFSDM filter handle. 01892 * @retval HAL status 01893 */ 01894 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 01895 { 01896 HAL_StatusTypeDef status = HAL_OK; 01897 01898 /* Check parameters */ 01899 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01900 01901 /* Check DFSDM filter state */ 01902 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ 01903 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) 01904 { 01905 /* Return error status */ 01906 status = HAL_ERROR; 01907 } 01908 else 01909 { 01910 /* Disable interrupts for regular conversions */ 01911 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); 01912 01913 /* Stop regular conversion */ 01914 DFSDM_RegConvStop(hdfsdm_filter); 01915 } 01916 /* Return function status */ 01917 return status; 01918 } 01919 01920 /** 01921 * @brief This function allows to start regular conversion in DMA mode. 01922 * @note This function should be called only when DFSDM filter instance is 01923 * in idle state or if injected conversion is ongoing. 01924 * Please note that data on buffer will contain signed regular conversion 01925 * value on 24 most significant bits and corresponding channel on 3 least 01926 * significant bits. 01927 * @param hdfsdm_filter DFSDM filter handle. 01928 * @param pData The destination buffer address. 01929 * @param Length The length of data to be transferred from DFSDM filter to memory. 01930 * @retval HAL status 01931 */ 01932 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 01933 int32_t *pData, 01934 uint32_t Length) 01935 { 01936 HAL_StatusTypeDef status = HAL_OK; 01937 01938 /* Check parameters */ 01939 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 01940 01941 /* Check destination address and length */ 01942 if((pData == NULL) || (Length == 0U)) 01943 { 01944 status = HAL_ERROR; 01945 } 01946 /* Check that DMA is enabled for regular conversion */ 01947 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) 01948 { 01949 status = HAL_ERROR; 01950 } 01951 /* Check parameters compatibility */ 01952 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ 01953 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ 01954 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ 01955 (Length != 1U)) 01956 { 01957 status = HAL_ERROR; 01958 } 01959 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ 01960 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ 01961 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) 01962 { 01963 status = HAL_ERROR; 01964 } 01965 /* Check DFSDM filter state */ 01966 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ 01967 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) 01968 { 01969 /* Set callbacks on DMA handler */ 01970 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; 01971 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; 01972 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ 01973 DFSDM_DMARegularHalfConvCplt : NULL; 01974 01975 /* Start DMA in interrupt mode */ 01976 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ 01977 (uint32_t) pData, Length) != HAL_OK) 01978 { 01979 /* Set DFSDM filter in error state */ 01980 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; 01981 status = HAL_ERROR; 01982 } 01983 else 01984 { 01985 /* Start regular conversion */ 01986 DFSDM_RegConvStart(hdfsdm_filter); 01987 } 01988 } 01989 else 01990 { 01991 status = HAL_ERROR; 01992 } 01993 /* Return function status */ 01994 return status; 01995 } 01996 01997 /** 01998 * @brief This function allows to start regular conversion in DMA mode and to get 01999 * only the 16 most significant bits of conversion. 02000 * @note This function should be called only when DFSDM filter instance is 02001 * in idle state or if injected conversion is ongoing. 02002 * Please note that data on buffer will contain signed 16 most significant 02003 * bits of regular conversion. 02004 * @param hdfsdm_filter DFSDM filter handle. 02005 * @param pData The destination buffer address. 02006 * @param Length The length of data to be transferred from DFSDM filter to memory. 02007 * @retval HAL status 02008 */ 02009 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02010 int16_t *pData, 02011 uint32_t Length) 02012 { 02013 HAL_StatusTypeDef status = HAL_OK; 02014 02015 /* Check parameters */ 02016 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02017 02018 /* Check destination address and length */ 02019 if((pData == NULL) || (Length == 0U)) 02020 { 02021 status = HAL_ERROR; 02022 } 02023 /* Check that DMA is enabled for regular conversion */ 02024 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) 02025 { 02026 status = HAL_ERROR; 02027 } 02028 /* Check parameters compatibility */ 02029 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ 02030 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ 02031 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ 02032 (Length != 1U)) 02033 { 02034 status = HAL_ERROR; 02035 } 02036 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ 02037 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ 02038 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) 02039 { 02040 status = HAL_ERROR; 02041 } 02042 /* Check DFSDM filter state */ 02043 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ 02044 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) 02045 { 02046 /* Set callbacks on DMA handler */ 02047 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; 02048 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; 02049 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ 02050 DFSDM_DMARegularHalfConvCplt : NULL; 02051 02052 /* Start DMA in interrupt mode */ 02053 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \ 02054 (uint32_t) pData, Length) != HAL_OK) 02055 { 02056 /* Set DFSDM filter in error state */ 02057 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; 02058 status = HAL_ERROR; 02059 } 02060 else 02061 { 02062 /* Start regular conversion */ 02063 DFSDM_RegConvStart(hdfsdm_filter); 02064 } 02065 } 02066 else 02067 { 02068 status = HAL_ERROR; 02069 } 02070 /* Return function status */ 02071 return status; 02072 } 02073 02074 /** 02075 * @brief This function allows to stop regular conversion in DMA mode. 02076 * @note This function should be called only if regular conversion is ongoing. 02077 * @param hdfsdm_filter DFSDM filter handle. 02078 * @retval HAL status 02079 */ 02080 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02081 { 02082 HAL_StatusTypeDef status = HAL_OK; 02083 02084 /* Check parameters */ 02085 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02086 02087 /* Check DFSDM filter state */ 02088 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ 02089 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) 02090 { 02091 /* Return error status */ 02092 status = HAL_ERROR; 02093 } 02094 else 02095 { 02096 /* Stop current DMA transfer */ 02097 if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) 02098 { 02099 /* Set DFSDM filter in error state */ 02100 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; 02101 status = HAL_ERROR; 02102 } 02103 else 02104 { 02105 /* Stop regular conversion */ 02106 DFSDM_RegConvStop(hdfsdm_filter); 02107 } 02108 } 02109 /* Return function status */ 02110 return status; 02111 } 02112 02113 /** 02114 * @brief This function allows to get regular conversion value. 02115 * @param hdfsdm_filter DFSDM filter handle. 02116 * @param Channel Corresponding channel of regular conversion. 02117 * @retval Regular conversion value 02118 */ 02119 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02120 uint32_t *Channel) 02121 { 02122 uint32_t reg = 0U; 02123 int32_t value = 0; 02124 02125 /* Check parameters */ 02126 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02127 assert_param(Channel != NULL); 02128 02129 /* Get value of data register for regular channel */ 02130 reg = hdfsdm_filter->Instance->FLTRDATAR; 02131 02132 /* Extract channel and regular conversion value */ 02133 *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); 02134 value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos); 02135 02136 /* return regular conversion value */ 02137 return value; 02138 } 02139 02140 /** 02141 * @brief This function allows to start injected conversion in polling mode. 02142 * @note This function should be called only when DFSDM filter instance is 02143 * in idle state or if regular conversion is ongoing. 02144 * @param hdfsdm_filter DFSDM filter handle. 02145 * @retval HAL status 02146 */ 02147 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02148 { 02149 HAL_StatusTypeDef status = HAL_OK; 02150 02151 /* Check parameters */ 02152 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02153 02154 /* Check DFSDM filter state */ 02155 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ 02156 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) 02157 { 02158 /* Start injected conversion */ 02159 DFSDM_InjConvStart(hdfsdm_filter); 02160 } 02161 else 02162 { 02163 status = HAL_ERROR; 02164 } 02165 /* Return function status */ 02166 return status; 02167 } 02168 02169 /** 02170 * @brief This function allows to poll for the end of injected conversion. 02171 * @note This function should be called only if injected conversion is ongoing. 02172 * @param hdfsdm_filter DFSDM filter handle. 02173 * @param Timeout Timeout value in milliseconds. 02174 * @retval HAL status 02175 */ 02176 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02177 uint32_t Timeout) 02178 { 02179 uint32_t tickstart; 02180 02181 /* Check parameters */ 02182 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02183 02184 /* Check DFSDM filter state */ 02185 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ 02186 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) 02187 { 02188 /* Return error status */ 02189 return HAL_ERROR; 02190 } 02191 else 02192 { 02193 /* Get timeout */ 02194 tickstart = HAL_GetTick(); 02195 02196 /* Wait end of injected conversions */ 02197 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) 02198 { 02199 /* Check the Timeout */ 02200 if(Timeout != HAL_MAX_DELAY) 02201 { 02202 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) 02203 { 02204 /* Return timeout status */ 02205 return HAL_TIMEOUT; 02206 } 02207 } 02208 } 02209 /* Check if overrun occurs */ 02210 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) 02211 { 02212 /* Update error code and call error callback */ 02213 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; 02214 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); 02215 02216 /* Clear injected overrun flag */ 02217 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; 02218 } 02219 02220 /* Update remaining injected conversions */ 02221 hdfsdm_filter->InjConvRemaining--; 02222 if(hdfsdm_filter->InjConvRemaining == 0U) 02223 { 02224 /* Update DFSDM filter state only if trigger is software */ 02225 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) 02226 { 02227 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ 02228 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; 02229 } 02230 02231 /* end of injected sequence, reset the value */ 02232 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ 02233 hdfsdm_filter->InjectedChannelsNbr : 1U; 02234 } 02235 02236 /* Return function status */ 02237 return HAL_OK; 02238 } 02239 } 02240 02241 /** 02242 * @brief This function allows to stop injected conversion in polling mode. 02243 * @note This function should be called only if injected conversion is ongoing. 02244 * @param hdfsdm_filter DFSDM filter handle. 02245 * @retval HAL status 02246 */ 02247 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02248 { 02249 HAL_StatusTypeDef status = HAL_OK; 02250 02251 /* Check parameters */ 02252 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02253 02254 /* Check DFSDM filter state */ 02255 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ 02256 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) 02257 { 02258 /* Return error status */ 02259 status = HAL_ERROR; 02260 } 02261 else 02262 { 02263 /* Stop injected conversion */ 02264 DFSDM_InjConvStop(hdfsdm_filter); 02265 } 02266 /* Return function status */ 02267 return status; 02268 } 02269 02270 /** 02271 * @brief This function allows to start injected conversion in interrupt mode. 02272 * @note This function should be called only when DFSDM filter instance is 02273 * in idle state or if regular conversion is ongoing. 02274 * @param hdfsdm_filter DFSDM filter handle. 02275 * @retval HAL status 02276 */ 02277 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02278 { 02279 HAL_StatusTypeDef status = HAL_OK; 02280 02281 /* Check parameters */ 02282 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02283 02284 /* Check DFSDM filter state */ 02285 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ 02286 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) 02287 { 02288 /* Enable interrupts for injected conversions */ 02289 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); 02290 02291 /* Start injected conversion */ 02292 DFSDM_InjConvStart(hdfsdm_filter); 02293 } 02294 else 02295 { 02296 status = HAL_ERROR; 02297 } 02298 /* Return function status */ 02299 return status; 02300 } 02301 02302 /** 02303 * @brief This function allows to stop injected conversion in interrupt mode. 02304 * @note This function should be called only if injected conversion is ongoing. 02305 * @param hdfsdm_filter DFSDM filter handle. 02306 * @retval HAL status 02307 */ 02308 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02309 { 02310 HAL_StatusTypeDef status = HAL_OK; 02311 02312 /* Check parameters */ 02313 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02314 02315 /* Check DFSDM filter state */ 02316 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ 02317 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) 02318 { 02319 /* Return error status */ 02320 status = HAL_ERROR; 02321 } 02322 else 02323 { 02324 /* Disable interrupts for injected conversions */ 02325 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); 02326 02327 /* Stop injected conversion */ 02328 DFSDM_InjConvStop(hdfsdm_filter); 02329 } 02330 /* Return function status */ 02331 return status; 02332 } 02333 02334 /** 02335 * @brief This function allows to start injected conversion in DMA mode. 02336 * @note This function should be called only when DFSDM filter instance is 02337 * in idle state or if regular conversion is ongoing. 02338 * Please note that data on buffer will contain signed injected conversion 02339 * value on 24 most significant bits and corresponding channel on 3 least 02340 * significant bits. 02341 * @param hdfsdm_filter DFSDM filter handle. 02342 * @param pData The destination buffer address. 02343 * @param Length The length of data to be transferred from DFSDM filter to memory. 02344 * @retval HAL status 02345 */ 02346 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02347 int32_t *pData, 02348 uint32_t Length) 02349 { 02350 HAL_StatusTypeDef status = HAL_OK; 02351 02352 /* Check parameters */ 02353 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02354 02355 /* Check destination address and length */ 02356 if((pData == NULL) || (Length == 0U)) 02357 { 02358 status = HAL_ERROR; 02359 } 02360 /* Check that DMA is enabled for injected conversion */ 02361 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) 02362 { 02363 status = HAL_ERROR; 02364 } 02365 /* Check parameters compatibility */ 02366 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ 02367 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ 02368 (Length > hdfsdm_filter->InjConvRemaining)) 02369 { 02370 status = HAL_ERROR; 02371 } 02372 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ 02373 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) 02374 { 02375 status = HAL_ERROR; 02376 } 02377 /* Check DFSDM filter state */ 02378 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ 02379 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) 02380 { 02381 /* Set callbacks on DMA handler */ 02382 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; 02383 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; 02384 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ 02385 DFSDM_DMAInjectedHalfConvCplt : NULL; 02386 02387 /* Start DMA in interrupt mode */ 02388 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ 02389 (uint32_t) pData, Length) != HAL_OK) 02390 { 02391 /* Set DFSDM filter in error state */ 02392 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; 02393 status = HAL_ERROR; 02394 } 02395 else 02396 { 02397 /* Start injected conversion */ 02398 DFSDM_InjConvStart(hdfsdm_filter); 02399 } 02400 } 02401 else 02402 { 02403 status = HAL_ERROR; 02404 } 02405 /* Return function status */ 02406 return status; 02407 } 02408 02409 /** 02410 * @brief This function allows to start injected conversion in DMA mode and to get 02411 * only the 16 most significant bits of conversion. 02412 * @note This function should be called only when DFSDM filter instance is 02413 * in idle state or if regular conversion is ongoing. 02414 * Please note that data on buffer will contain signed 16 most significant 02415 * bits of injected conversion. 02416 * @param hdfsdm_filter DFSDM filter handle. 02417 * @param pData The destination buffer address. 02418 * @param Length The length of data to be transferred from DFSDM filter to memory. 02419 * @retval HAL status 02420 */ 02421 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02422 int16_t *pData, 02423 uint32_t Length) 02424 { 02425 HAL_StatusTypeDef status = HAL_OK; 02426 02427 /* Check parameters */ 02428 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02429 02430 /* Check destination address and length */ 02431 if((pData == NULL) || (Length == 0U)) 02432 { 02433 status = HAL_ERROR; 02434 } 02435 /* Check that DMA is enabled for injected conversion */ 02436 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) 02437 { 02438 status = HAL_ERROR; 02439 } 02440 /* Check parameters compatibility */ 02441 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ 02442 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ 02443 (Length > hdfsdm_filter->InjConvRemaining)) 02444 { 02445 status = HAL_ERROR; 02446 } 02447 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ 02448 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) 02449 { 02450 status = HAL_ERROR; 02451 } 02452 /* Check DFSDM filter state */ 02453 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ 02454 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) 02455 { 02456 /* Set callbacks on DMA handler */ 02457 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; 02458 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; 02459 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ 02460 DFSDM_DMAInjectedHalfConvCplt : NULL; 02461 02462 /* Start DMA in interrupt mode */ 02463 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \ 02464 (uint32_t) pData, Length) != HAL_OK) 02465 { 02466 /* Set DFSDM filter in error state */ 02467 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; 02468 status = HAL_ERROR; 02469 } 02470 else 02471 { 02472 /* Start injected conversion */ 02473 DFSDM_InjConvStart(hdfsdm_filter); 02474 } 02475 } 02476 else 02477 { 02478 status = HAL_ERROR; 02479 } 02480 /* Return function status */ 02481 return status; 02482 } 02483 02484 /** 02485 * @brief This function allows to stop injected conversion in DMA mode. 02486 * @note This function should be called only if injected conversion is ongoing. 02487 * @param hdfsdm_filter DFSDM filter handle. 02488 * @retval HAL status 02489 */ 02490 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02491 { 02492 HAL_StatusTypeDef status = HAL_OK; 02493 02494 /* Check parameters */ 02495 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02496 02497 /* Check DFSDM filter state */ 02498 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ 02499 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) 02500 { 02501 /* Return error status */ 02502 status = HAL_ERROR; 02503 } 02504 else 02505 { 02506 /* Stop current DMA transfer */ 02507 if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) 02508 { 02509 /* Set DFSDM filter in error state */ 02510 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; 02511 status = HAL_ERROR; 02512 } 02513 else 02514 { 02515 /* Stop regular conversion */ 02516 DFSDM_InjConvStop(hdfsdm_filter); 02517 } 02518 } 02519 /* Return function status */ 02520 return status; 02521 } 02522 02523 /** 02524 * @brief This function allows to get injected conversion value. 02525 * @param hdfsdm_filter DFSDM filter handle. 02526 * @param Channel Corresponding channel of injected conversion. 02527 * @retval Injected conversion value 02528 */ 02529 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02530 uint32_t *Channel) 02531 { 02532 uint32_t reg = 0U; 02533 int32_t value = 0; 02534 02535 /* Check parameters */ 02536 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02537 assert_param(Channel != NULL); 02538 02539 /* Get value of data register for injected channel */ 02540 reg = hdfsdm_filter->Instance->FLTJDATAR; 02541 02542 /* Extract channel and injected conversion value */ 02543 *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); 02544 value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos); 02545 02546 /* return regular conversion value */ 02547 return value; 02548 } 02549 02550 /** 02551 * @brief This function allows to start filter analog watchdog in interrupt mode. 02552 * @param hdfsdm_filter DFSDM filter handle. 02553 * @param awdParam DFSDM filter analog watchdog parameters. 02554 * @retval HAL status 02555 */ 02556 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02557 DFSDM_Filter_AwdParamTypeDef *awdParam) 02558 { 02559 HAL_StatusTypeDef status = HAL_OK; 02560 02561 /* Check parameters */ 02562 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02563 assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource)); 02564 assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel)); 02565 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold)); 02566 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold)); 02567 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal)); 02568 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal)); 02569 02570 /* Check DFSDM filter state */ 02571 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ 02572 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) 02573 { 02574 /* Return error status */ 02575 status = HAL_ERROR; 02576 } 02577 else 02578 { 02579 /* Set analog watchdog data source */ 02580 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL); 02581 hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource; 02582 02583 /* Set thresholds and break signals */ 02584 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); 02585 hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \ 02586 awdParam->HighBreakSignal); 02587 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); 02588 hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \ 02589 awdParam->LowBreakSignal); 02590 02591 /* Set channels and interrupt for analog watchdog */ 02592 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); 02593 hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \ 02594 DFSDM_FLTCR2_AWDIE); 02595 } 02596 /* Return function status */ 02597 return status; 02598 } 02599 02600 /** 02601 * @brief This function allows to stop filter analog watchdog in interrupt mode. 02602 * @param hdfsdm_filter DFSDM filter handle. 02603 * @retval HAL status 02604 */ 02605 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02606 { 02607 HAL_StatusTypeDef status = HAL_OK; 02608 02609 /* Check parameters */ 02610 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02611 02612 /* Check DFSDM filter state */ 02613 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ 02614 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) 02615 { 02616 /* Return error status */ 02617 status = HAL_ERROR; 02618 } 02619 else 02620 { 02621 /* Reset channels for analog watchdog and deactivate interrupt */ 02622 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE); 02623 02624 /* Clear all analog watchdog flags */ 02625 hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF); 02626 02627 /* Reset thresholds and break signals */ 02628 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); 02629 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); 02630 02631 /* Reset analog watchdog data source */ 02632 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL); 02633 } 02634 /* Return function status */ 02635 return status; 02636 } 02637 02638 /** 02639 * @brief This function allows to start extreme detector feature. 02640 * @param hdfsdm_filter DFSDM filter handle. 02641 * @param Channel Channels where extreme detector is enabled. 02642 * This parameter can be a values combination of @ref DFSDM_Channel_Selection. 02643 * @retval HAL status 02644 */ 02645 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02646 uint32_t Channel) 02647 { 02648 HAL_StatusTypeDef status = HAL_OK; 02649 02650 /* Check parameters */ 02651 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02652 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); 02653 02654 /* Check DFSDM filter state */ 02655 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ 02656 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) 02657 { 02658 /* Return error status */ 02659 status = HAL_ERROR; 02660 } 02661 else 02662 { 02663 /* Set channels for extreme detector */ 02664 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); 02665 hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); 02666 } 02667 /* Return function status */ 02668 return status; 02669 } 02670 02671 /** 02672 * @brief This function allows to stop extreme detector feature. 02673 * @param hdfsdm_filter DFSDM filter handle. 02674 * @retval HAL status 02675 */ 02676 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02677 { 02678 HAL_StatusTypeDef status = HAL_OK; 02679 __IO uint32_t reg1; 02680 __IO uint32_t reg2; 02681 02682 /* Check parameters */ 02683 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02684 02685 /* Check DFSDM filter state */ 02686 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ 02687 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) 02688 { 02689 /* Return error status */ 02690 status = HAL_ERROR; 02691 } 02692 else 02693 { 02694 /* Reset channels for extreme detector */ 02695 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); 02696 02697 /* Clear extreme detector values */ 02698 reg1 = hdfsdm_filter->Instance->FLTEXMAX; 02699 reg2 = hdfsdm_filter->Instance->FLTEXMIN; 02700 UNUSED(reg1); /* To avoid GCC warning */ 02701 UNUSED(reg2); /* To avoid GCC warning */ 02702 } 02703 /* Return function status */ 02704 return status; 02705 } 02706 02707 /** 02708 * @brief This function allows to get extreme detector maximum value. 02709 * @param hdfsdm_filter DFSDM filter handle. 02710 * @param Channel Corresponding channel. 02711 * @retval Extreme detector maximum value 02712 * This value is between Min_Data = -8388608 and Max_Data = 8388607. 02713 */ 02714 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02715 uint32_t *Channel) 02716 { 02717 uint32_t reg = 0U; 02718 int32_t value = 0; 02719 02720 /* Check parameters */ 02721 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02722 assert_param(Channel != NULL); 02723 02724 /* Get value of extreme detector maximum register */ 02725 reg = hdfsdm_filter->Instance->FLTEXMAX; 02726 02727 /* Extract channel and extreme detector maximum value */ 02728 *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); 02729 value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos); 02730 02731 /* return extreme detector maximum value */ 02732 return value; 02733 } 02734 02735 /** 02736 * @brief This function allows to get extreme detector minimum value. 02737 * @param hdfsdm_filter DFSDM filter handle. 02738 * @param Channel Corresponding channel. 02739 * @retval Extreme detector minimum value 02740 * This value is between Min_Data = -8388608 and Max_Data = 8388607. 02741 */ 02742 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 02743 uint32_t *Channel) 02744 { 02745 uint32_t reg = 0U; 02746 int32_t value = 0; 02747 02748 /* Check parameters */ 02749 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02750 assert_param(Channel != NULL); 02751 02752 /* Get value of extreme detector minimum register */ 02753 reg = hdfsdm_filter->Instance->FLTEXMIN; 02754 02755 /* Extract channel and extreme detector minimum value */ 02756 *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); 02757 value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos); 02758 02759 /* return extreme detector minimum value */ 02760 return value; 02761 } 02762 02763 /** 02764 * @brief This function allows to get conversion time value. 02765 * @param hdfsdm_filter DFSDM filter handle. 02766 * @retval Conversion time value 02767 * @note To get time in second, this value has to be divided by DFSDM clock frequency. 02768 */ 02769 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02770 { 02771 uint32_t reg = 0U; 02772 uint32_t value = 0U; 02773 02774 /* Check parameters */ 02775 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); 02776 02777 /* Get value of conversion timer register */ 02778 reg = hdfsdm_filter->Instance->FLTCNVTIMR; 02779 02780 /* Extract conversion time value */ 02781 value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos); 02782 02783 /* return extreme detector minimum value */ 02784 return value; 02785 } 02786 02787 /** 02788 * @brief This function handles the DFSDM interrupts. 02789 * @param hdfsdm_filter DFSDM filter handle. 02790 * @retval None 02791 */ 02792 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 02793 { 02794 /* Check if overrun occurs during regular conversion */ 02795 if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0U) && \ 02796 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0U)) 02797 { 02798 /* Clear regular overrun flag */ 02799 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; 02800 02801 /* Update error code */ 02802 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; 02803 02804 /* Call error callback */ 02805 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); 02806 } 02807 /* Check if overrun occurs during injected conversion */ 02808 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0U) && \ 02809 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0U)) 02810 { 02811 /* Clear injected overrun flag */ 02812 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; 02813 02814 /* Update error code */ 02815 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; 02816 02817 /* Call error callback */ 02818 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); 02819 } 02820 /* Check if end of regular conversion */ 02821 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0U) && \ 02822 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0U)) 02823 { 02824 /* Call regular conversion complete callback */ 02825 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); 02826 02827 /* End of conversion if mode is not continuous and software trigger */ 02828 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ 02829 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) 02830 { 02831 /* Disable interrupts for regular conversions */ 02832 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE); 02833 02834 /* Update DFSDM filter state */ 02835 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ 02836 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; 02837 } 02838 } 02839 /* Check if end of injected conversion */ 02840 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0U) && \ 02841 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0U)) 02842 { 02843 /* Call injected conversion complete callback */ 02844 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); 02845 02846 /* Update remaining injected conversions */ 02847 hdfsdm_filter->InjConvRemaining--; 02848 if(hdfsdm_filter->InjConvRemaining == 0U) 02849 { 02850 /* End of conversion if trigger is software */ 02851 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) 02852 { 02853 /* Disable interrupts for injected conversions */ 02854 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE); 02855 02856 /* Update DFSDM filter state */ 02857 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ 02858 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; 02859 } 02860 /* end of injected sequence, reset the value */ 02861 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ 02862 hdfsdm_filter->InjectedChannelsNbr : 1U; 02863 } 02864 } 02865 /* Check if analog watchdog occurs */ 02866 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0U) && \ 02867 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0U)) 02868 { 02869 uint32_t reg = 0U; 02870 uint32_t threshold = 0U; 02871 uint32_t channel = 0U; 02872 02873 /* Get channel and threshold */ 02874 reg = hdfsdm_filter->Instance->FLTAWSR; 02875 threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; 02876 if(threshold == DFSDM_AWD_HIGH_THRESHOLD) 02877 { 02878 reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos; 02879 } 02880 while((reg & 1U) == 0U) 02881 { 02882 channel++; 02883 reg = reg >> 1U; 02884 } 02885 /* Clear analog watchdog flag */ 02886 hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ 02887 (1U << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ 02888 (1U << channel); 02889 02890 /* Call analog watchdog callback */ 02891 HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold); 02892 } 02893 /* Check if clock absence occurs */ 02894 else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ 02895 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \ 02896 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U)) 02897 { 02898 uint32_t reg = 0U; 02899 uint32_t channel = 0U; 02900 02901 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); 02902 02903 while(channel < DFSDM1_CHANNEL_NUMBER) 02904 { 02905 /* Check if flag is set and corresponding channel is enabled */ 02906 if(((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL)) 02907 { 02908 /* Check clock absence has been enabled for this channel */ 02909 if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U) 02910 { 02911 /* Clear clock absence flag */ 02912 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 02913 02914 /* Call clock absence callback */ 02915 HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); 02916 } 02917 } 02918 channel++; 02919 reg = reg >> 1U; 02920 } 02921 } 02922 #if defined (DFSDM2_Channel0) 02923 /* Check if clock absence occurs */ 02924 else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \ 02925 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \ 02926 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U)) 02927 { 02928 uint32_t reg = 0U; 02929 uint32_t channel = 0U; 02930 02931 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); 02932 02933 while(channel < DFSDM2_CHANNEL_NUMBER) 02934 { 02935 /* Check if flag is set and corresponding channel is enabled */ 02936 if(((reg & 1U) != 0U) && (a_dfsdm2ChannelHandle[channel] != NULL)) 02937 { 02938 /* Check clock absence has been enabled for this channel */ 02939 if((a_dfsdm2ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U) 02940 { 02941 /* Clear clock absence flag */ 02942 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); 02943 02944 /* Call clock absence callback */ 02945 HAL_DFSDM_ChannelCkabCallback(a_dfsdm2ChannelHandle[channel]); 02946 } 02947 } 02948 channel++; 02949 reg = reg >> 1U; 02950 } 02951 } 02952 #endif /* DFSDM2_Channel0 */ 02953 /* Check if short circuit detection occurs */ 02954 else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ 02955 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \ 02956 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U)) 02957 { 02958 uint32_t reg = 0U; 02959 uint32_t channel = 0U; 02960 02961 /* Get channel */ 02962 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); 02963 while((reg & 1U) == 0U) 02964 { 02965 channel++; 02966 reg = reg >> 1U; 02967 } 02968 02969 /* Clear short circuit detection flag */ 02970 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); 02971 02972 /* Call short circuit detection callback */ 02973 HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); 02974 } 02975 #if defined (DFSDM2_Channel0) 02976 /* Check if short circuit detection occurs */ 02977 else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \ 02978 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \ 02979 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U)) 02980 { 02981 uint32_t reg = 0U; 02982 uint32_t channel = 0U; 02983 02984 /* Get channel */ 02985 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); 02986 while((reg & 1U) == 0U) 02987 { 02988 channel++; 02989 reg = reg >> 1U; 02990 } 02991 02992 /* Clear short circuit detection flag */ 02993 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel)); 02994 02995 /* Call short circuit detection callback */ 02996 HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]); 02997 } 02998 #endif /* DFSDM2_Channel0 */ 02999 } 03000 03001 /** 03002 * @brief Regular conversion complete callback. 03003 * @note In interrupt mode, user has to read conversion value in this function 03004 * using HAL_DFSDM_FilterGetRegularValue. 03005 * @param hdfsdm_filter DFSDM filter handle. 03006 * @retval None 03007 */ 03008 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 03009 { 03010 /* Prevent unused argument(s) compilation warning */ 03011 UNUSED(hdfsdm_filter); 03012 /* NOTE : This function should not be modified, when the callback is needed, 03013 the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file. 03014 */ 03015 } 03016 03017 /** 03018 * @brief Half regular conversion complete callback. 03019 * @param hdfsdm_filter DFSDM filter handle. 03020 * @retval None 03021 */ 03022 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 03023 { 03024 /* Prevent unused argument(s) compilation warning */ 03025 UNUSED(hdfsdm_filter); 03026 /* NOTE : This function should not be modified, when the callback is needed, 03027 the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file. 03028 */ 03029 } 03030 03031 /** 03032 * @brief Injected conversion complete callback. 03033 * @note In interrupt mode, user has to read conversion value in this function 03034 * using HAL_DFSDM_FilterGetInjectedValue. 03035 * @param hdfsdm_filter DFSDM filter handle. 03036 * @retval None 03037 */ 03038 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 03039 { 03040 /* Prevent unused argument(s) compilation warning */ 03041 UNUSED(hdfsdm_filter); 03042 /* NOTE : This function should not be modified, when the callback is needed, 03043 the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file. 03044 */ 03045 } 03046 03047 /** 03048 * @brief Half injected conversion complete callback. 03049 * @param hdfsdm_filter DFSDM filter handle. 03050 * @retval None 03051 */ 03052 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 03053 { 03054 /* Prevent unused argument(s) compilation warning */ 03055 UNUSED(hdfsdm_filter); 03056 /* NOTE : This function should not be modified, when the callback is needed, 03057 the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file. 03058 */ 03059 } 03060 03061 /** 03062 * @brief Filter analog watchdog callback. 03063 * @param hdfsdm_filter DFSDM filter handle. 03064 * @param Channel Corresponding channel. 03065 * @param Threshold Low or high threshold has been reached. 03066 * @retval None 03067 */ 03068 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 03069 uint32_t Channel, uint32_t Threshold) 03070 { 03071 /* Prevent unused argument(s) compilation warning */ 03072 UNUSED(hdfsdm_filter); 03073 UNUSED(Channel); 03074 UNUSED(Threshold); 03075 03076 /* NOTE : This function should not be modified, when the callback is needed, 03077 the HAL_DFSDM_FilterAwdCallback could be implemented in the user file. 03078 */ 03079 } 03080 03081 /** 03082 * @brief Error callback. 03083 * @param hdfsdm_filter DFSDM filter handle. 03084 * @retval None 03085 */ 03086 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 03087 { 03088 /* Prevent unused argument(s) compilation warning */ 03089 UNUSED(hdfsdm_filter); 03090 /* NOTE : This function should not be modified, when the callback is needed, 03091 the HAL_DFSDM_FilterErrorCallback could be implemented in the user file. 03092 */ 03093 } 03094 03095 /** 03096 * @} 03097 */ 03098 03099 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 03100 * @brief Filter state functions 03101 * 03102 @verbatim 03103 ============================================================================== 03104 ##### Filter state functions ##### 03105 ============================================================================== 03106 [..] This section provides functions allowing to: 03107 (+) Get the DFSDM filter state. 03108 (+) Get the DFSDM filter error. 03109 @endverbatim 03110 * @{ 03111 */ 03112 03113 /** 03114 * @brief This function allows to get the current DFSDM filter handle state. 03115 * @param hdfsdm_filter DFSDM filter handle. 03116 * @retval DFSDM filter state. 03117 */ 03118 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 03119 { 03120 /* Return DFSDM filter handle state */ 03121 return hdfsdm_filter->State; 03122 } 03123 03124 /** 03125 * @brief This function allows to get the current DFSDM filter error. 03126 * @param hdfsdm_filter DFSDM filter handle. 03127 * @retval DFSDM filter error code. 03128 */ 03129 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) 03130 { 03131 return hdfsdm_filter->ErrorCode; 03132 } 03133 03134 /** 03135 * @} 03136 */ 03137 03138 /** @defgroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions 03139 * @brief Filter state functions 03140 * 03141 @verbatim 03142 ============================================================================== 03143 ##### Filter MultiChannel operation functions ##### 03144 ============================================================================== 03145 [..] This section provides functions allowing to: 03146 (+) Control the DFSDM Multi channel delay block 03147 @endverbatim 03148 * @{ 03149 */ 03150 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 03151 /** 03152 * @brief Select the DFSDM2 as clock source for the bitstream clock. 03153 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called 03154 * before HAL_DFSDM_BitstreamClock_Start() 03155 */ 03156 void HAL_DFSDM_BitstreamClock_Start(void) 03157 { 03158 uint32_t tmp = 0; 03159 03160 tmp = SYSCFG->MCHDLYCR; 03161 tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL)); 03162 03163 SYSCFG->MCHDLYCR = (tmp|SYSCFG_MCHDLYCR_BSCKSEL); 03164 } 03165 03166 /** 03167 * @brief Stop the DFSDM2 as clock source for the bitstream clock. 03168 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called 03169 * before HAL_DFSDM_BitstreamClock_Stop() 03170 * @retval None 03171 */ 03172 void HAL_DFSDM_BitstreamClock_Stop(void) 03173 { 03174 uint32_t tmp = 0U; 03175 03176 tmp = SYSCFG->MCHDLYCR; 03177 tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL)); 03178 03179 SYSCFG->MCHDLYCR = tmp; 03180 } 03181 03182 /** 03183 * @brief Disable Delay Clock for DFSDM1/2. 03184 * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2. 03185 * HAL_MCHDLY_CLOCK_DFSDM1. 03186 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called 03187 * before HAL_DFSDM_DisableDelayClock() 03188 * @retval None 03189 */ 03190 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY) 03191 { 03192 uint32_t tmp = 0U; 03193 03194 assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY)); 03195 03196 tmp = SYSCFG->MCHDLYCR; 03197 if(MCHDLY == HAL_MCHDLY_CLOCK_DFSDM2) 03198 { 03199 tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY2EN); 03200 } 03201 else 03202 { 03203 tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY1EN); 03204 } 03205 03206 SYSCFG->MCHDLYCR = tmp; 03207 } 03208 03209 /** 03210 * @brief Enable Delay Clock for DFSDM1/2. 03211 * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2. 03212 * HAL_MCHDLY_CLOCK_DFSDM1. 03213 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called 03214 * before HAL_DFSDM_EnableDelayClock() 03215 * @retval None 03216 */ 03217 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY) 03218 { 03219 uint32_t tmp = 0U; 03220 03221 assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY)); 03222 03223 tmp = SYSCFG->MCHDLYCR; 03224 tmp = tmp & ~MCHDLY; 03225 03226 SYSCFG->MCHDLYCR = (tmp|MCHDLY); 03227 } 03228 03229 /** 03230 * @brief Select the source for CKin signals for DFSDM1/2. 03231 * @param source DFSDM2_CKIN_PAD. 03232 * DFSDM2_CKIN_DM. 03233 * DFSDM1_CKIN_PAD. 03234 * DFSDM1_CKIN_DM. 03235 * @retval None 03236 */ 03237 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source) 03238 { 03239 uint32_t tmp = 0U; 03240 03241 assert_param(IS_DFSDM_CLOCKIN_SELECTION(source)); 03242 03243 tmp = SYSCFG->MCHDLYCR; 03244 03245 if((source == HAL_DFSDM2_CKIN_PAD) || (source == HAL_DFSDM2_CKIN_DM)) 03246 { 03247 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG); 03248 03249 if(source == HAL_DFSDM2_CKIN_PAD) 03250 { 03251 source = 0x000000U; 03252 } 03253 } 03254 else 03255 { 03256 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CFG); 03257 } 03258 03259 SYSCFG->MCHDLYCR = (source|tmp); 03260 } 03261 03262 /** 03263 * @brief Select the source for CKOut signals for DFSDM1/2. 03264 * @param source: DFSDM2_CKOUT_DFSDM2. 03265 * DFSDM2_CKOUT_M27. 03266 * DFSDM1_CKOUT_DFSDM1. 03267 * DFSDM1_CKOUT_M27. 03268 * @retval None 03269 */ 03270 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source) 03271 { 03272 uint32_t tmp = 0U; 03273 03274 assert_param(IS_DFSDM_CLOCKOUT_SELECTION(source)); 03275 03276 tmp = SYSCFG->MCHDLYCR; 03277 03278 if((source == HAL_DFSDM2_CKOUT_DFSDM2) || (source == HAL_DFSDM2_CKOUT_M27)) 03279 { 03280 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL); 03281 03282 if(source == HAL_DFSDM2_CKOUT_DFSDM2) 03283 { 03284 source = 0x000U; 03285 } 03286 } 03287 else 03288 { 03289 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CKOSEL); 03290 } 03291 03292 SYSCFG->MCHDLYCR = (source|tmp); 03293 } 03294 03295 /** 03296 * @brief Select the source for DataIn0 signals for DFSDM1/2. 03297 * @param source DATAIN0_DFSDM2_PAD. 03298 * DATAIN0_DFSDM2_DATAIN1. 03299 * DATAIN0_DFSDM1_PAD. 03300 * DATAIN0_DFSDM1_DATAIN1. 03301 * @retval None 03302 */ 03303 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source) 03304 { 03305 uint32_t tmp = 0U; 03306 03307 assert_param(IS_DFSDM_DATAIN0_SRC_SELECTION(source)); 03308 03309 tmp = SYSCFG->MCHDLYCR; 03310 03311 if((source == HAL_DATAIN0_DFSDM2_PAD)|| (source == HAL_DATAIN0_DFSDM2_DATAIN1)) 03312 { 03313 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL); 03314 if(source == HAL_DATAIN0_DFSDM2_PAD) 03315 { 03316 source = 0x00000U; 03317 } 03318 } 03319 else 03320 { 03321 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D0SEL); 03322 } 03323 SYSCFG->MCHDLYCR = (source|tmp); 03324 } 03325 03326 /** 03327 * @brief Select the source for DataIn2 signals for DFSDM1/2. 03328 * @param source DATAIN2_DFSDM2_PAD. 03329 * DATAIN2_DFSDM2_DATAIN3. 03330 * DATAIN2_DFSDM1_PAD. 03331 * DATAIN2_DFSDM1_DATAIN3. 03332 * @retval None 03333 */ 03334 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source) 03335 { 03336 uint32_t tmp = 0U; 03337 03338 assert_param(IS_DFSDM_DATAIN2_SRC_SELECTION(source)); 03339 03340 tmp = SYSCFG->MCHDLYCR; 03341 03342 if((source == HAL_DATAIN2_DFSDM2_PAD)|| (source == HAL_DATAIN2_DFSDM2_DATAIN3)) 03343 { 03344 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL); 03345 if (source == HAL_DATAIN2_DFSDM2_PAD) 03346 { 03347 source = 0x0000U; 03348 } 03349 } 03350 else 03351 { 03352 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D2SEL); 03353 } 03354 SYSCFG->MCHDLYCR = (source|tmp); 03355 } 03356 03357 /** 03358 * @brief Select the source for DataIn4 signals for DFSDM2. 03359 * @param source DATAIN4_DFSDM2_PAD. 03360 * DATAIN4_DFSDM2_DATAIN5 03361 * @retval None 03362 */ 03363 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source) 03364 { 03365 uint32_t tmp = 0U; 03366 03367 assert_param(IS_DFSDM_DATAIN4_SRC_SELECTION(source)); 03368 03369 tmp = SYSCFG->MCHDLYCR; 03370 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D4SEL); 03371 03372 SYSCFG->MCHDLYCR = (source|tmp); 03373 } 03374 03375 /** 03376 * @brief Select the source for DataIn6 signals for DFSDM2. 03377 * @param source DATAIN6_DFSDM2_PAD. 03378 * DATAIN6_DFSDM2_DATAIN7. 03379 * @retval None 03380 */ 03381 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source) 03382 { 03383 uint32_t tmp = 0U; 03384 03385 assert_param(IS_DFSDM_DATAIN6_SRC_SELECTION(source)); 03386 03387 tmp = SYSCFG->MCHDLYCR; 03388 03389 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL); 03390 03391 SYSCFG->MCHDLYCR = (source|tmp); 03392 } 03393 03394 /** 03395 * @brief Configure the distribution of the bitstream clock gated from TIM4_OC 03396 * for DFSDM1 or TIM3_OC for DFSDM2 03397 * @param source DFSDM1_CLKIN0_TIM4OC2 03398 * DFSDM1_CLKIN2_TIM4OC2 03399 * DFSDM1_CLKIN1_TIM4OC1 03400 * DFSDM1_CLKIN3_TIM4OC1 03401 * DFSDM2_CLKIN0_TIM3OC4 03402 * DFSDM2_CLKIN4_TIM3OC4 03403 * DFSDM2_CLKIN1_TIM3OC3 03404 * DFSDM2_CLKIN5_TIM3OC3 03405 * DFSDM2_CLKIN2_TIM3OC2 03406 * DFSDM2_CLKIN6_TIM3OC2 03407 * DFSDM2_CLKIN3_TIM3OC1 03408 * DFSDM2_CLKIN7_TIM3OC1 03409 * @retval None 03410 */ 03411 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source) 03412 { 03413 uint32_t tmp = 0U; 03414 03415 assert_param(IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(source)); 03416 03417 tmp = SYSCFG->MCHDLYCR; 03418 03419 if ((source == HAL_DFSDM1_CLKIN0_TIM4OC2) || (source == HAL_DFSDM1_CLKIN2_TIM4OC2)) 03420 { 03421 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK02SEL); 03422 } 03423 else if ((source == HAL_DFSDM1_CLKIN1_TIM4OC1) || (source == HAL_DFSDM1_CLKIN3_TIM4OC1)) 03424 { 03425 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK13SEL); 03426 } 03427 else if ((source == HAL_DFSDM2_CLKIN0_TIM3OC4) || (source == HAL_DFSDM2_CLKIN4_TIM3OC4)) 03428 { 03429 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK04SEL); 03430 } 03431 else if ((source == HAL_DFSDM2_CLKIN1_TIM3OC3) || (source == HAL_DFSDM2_CLKIN5_TIM3OC3)) 03432 { 03433 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL); 03434 03435 }else if ((source == HAL_DFSDM2_CLKIN2_TIM3OC2) || (source == HAL_DFSDM2_CLKIN6_TIM3OC2)) 03436 { 03437 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL); 03438 } 03439 else 03440 { 03441 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL); 03442 } 03443 03444 if((source == HAL_DFSDM1_CLKIN0_TIM4OC2) ||(source == HAL_DFSDM1_CLKIN1_TIM4OC1)|| 03445 (source == HAL_DFSDM2_CLKIN0_TIM3OC4) ||(source == HAL_DFSDM2_CLKIN1_TIM3OC3)|| 03446 (source == HAL_DFSDM2_CLKIN2_TIM3OC2) ||(source == HAL_DFSDM2_CLKIN3_TIM3OC1)) 03447 { 03448 source = 0x0000U; 03449 } 03450 03451 SYSCFG->MCHDLYCR = (source|tmp); 03452 } 03453 03454 /** 03455 * @brief Configure multi channel delay block: Use DFSDM2 audio clock source as input 03456 * clock for DFSDM1 and DFSDM2 filters to Synchronize DFSDMx filters. 03457 * Set the path of the DFSDM2 clock output (dfsdm2_ckout) to the 03458 * DFSDM1/2 CkInx and data inputs channels by configuring following MCHDLY muxes 03459 * or demuxes: M1, M2, M3, M4, M5, M6, M7, M8, DM1, DM2, DM3, DM4, DM5, DM6, 03460 * M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 based on the 03461 * contains of the DFSDM_MultiChannelConfigTypeDef structure 03462 * @param mchdlystruct Structure of multi channel configuration 03463 * @retval None 03464 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called 03465 * before HAL_DFSDM_ConfigMultiChannelDelay() 03466 * @note The HAL_DFSDM_ConfigMultiChannelDelay() function clears the SYSCFG-MCHDLYCR 03467 * register before setting the new configuration. 03468 */ 03469 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct) 03470 { 03471 uint32_t mchdlyreg = 0U; 03472 03473 assert_param(IS_DFSDM_DFSDM1_CLKOUT(mchdlystruct->DFSDM1ClockOut)); 03474 assert_param(IS_DFSDM_DFSDM2_CLKOUT(mchdlystruct->DFSDM2ClockOut)); 03475 assert_param(IS_DFSDM_DFSDM1_CLKIN(mchdlystruct->DFSDM1ClockIn)); 03476 assert_param(IS_DFSDM_DFSDM2_CLKIN(mchdlystruct->DFSDM2ClockIn)); 03477 assert_param(IS_DFSDM_DFSDM1_BIT_CLK((mchdlystruct->DFSDM1BitClkDistribution))); 03478 assert_param(IS_DFSDM_DFSDM2_BIT_CLK(mchdlystruct->DFSDM2BitClkDistribution)); 03479 assert_param(IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(mchdlystruct->DFSDM1DataDistribution)); 03480 assert_param(IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(mchdlystruct->DFSDM2DataDistribution)); 03481 03482 mchdlyreg = (SYSCFG->MCHDLYCR & 0x80103U); 03483 03484 SYSCFG->MCHDLYCR = (mchdlyreg |(mchdlystruct->DFSDM1ClockOut)|(mchdlystruct->DFSDM2ClockOut)| 03485 (mchdlystruct->DFSDM1ClockIn)|(mchdlystruct->DFSDM2ClockIn)| 03486 (mchdlystruct->DFSDM1BitClkDistribution)| (mchdlystruct->DFSDM2BitClkDistribution)| 03487 (mchdlystruct->DFSDM1DataDistribution)| (mchdlystruct->DFSDM2DataDistribution)); 03488 03489 } 03490 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ 03491 /** 03492 * @} 03493 */ 03494 /** 03495 * @} 03496 */ 03497 /* End of exported functions -------------------------------------------------*/ 03498 03499 /* Private functions ---------------------------------------------------------*/ 03500 /** @addtogroup DFSDM_Private_Functions DFSDM Private Functions 03501 * @{ 03502 */ 03503 03504 /** 03505 * @brief DMA half transfer complete callback for regular conversion. 03506 * @param hdma DMA handle. 03507 * @retval None 03508 */ 03509 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) 03510 { 03511 /* Get DFSDM filter handle */ 03512 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; 03513 03514 /* Call regular half conversion complete callback */ 03515 HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter); 03516 } 03517 03518 /** 03519 * @brief DMA transfer complete callback for regular conversion. 03520 * @param hdma DMA handle. 03521 * @retval None 03522 */ 03523 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) 03524 { 03525 /* Get DFSDM filter handle */ 03526 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; 03527 03528 /* Call regular conversion complete callback */ 03529 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); 03530 } 03531 03532 /** 03533 * @brief DMA half transfer complete callback for injected conversion. 03534 * @param hdma DMA handle. 03535 * @retval None 03536 */ 03537 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) 03538 { 03539 /* Get DFSDM filter handle */ 03540 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; 03541 03542 /* Call injected half conversion complete callback */ 03543 HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter); 03544 } 03545 03546 /** 03547 * @brief DMA transfer complete callback for injected conversion. 03548 * @param hdma DMA handle. 03549 * @retval None 03550 */ 03551 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) 03552 { 03553 /* Get DFSDM filter handle */ 03554 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; 03555 03556 /* Call injected conversion complete callback */ 03557 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); 03558 } 03559 03560 /** 03561 * @brief DMA error callback. 03562 * @param hdma DMA handle. 03563 * @retval None 03564 */ 03565 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) 03566 { 03567 /* Get DFSDM filter handle */ 03568 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; 03569 03570 /* Update error code */ 03571 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA; 03572 03573 /* Call error callback */ 03574 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); 03575 } 03576 03577 /** 03578 * @brief This function allows to get the number of injected channels. 03579 * @param Channels bitfield of injected channels. 03580 * @retval Number of injected channels. 03581 */ 03582 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) 03583 { 03584 uint32_t nbChannels = 0U; 03585 uint32_t tmp; 03586 03587 /* Get the number of channels from bitfield */ 03588 tmp = (uint32_t) (Channels & DFSDM_LSB_MASK); 03589 while(tmp != 0U) 03590 { 03591 if((tmp & 1U) != 0U) 03592 { 03593 nbChannels++; 03594 } 03595 tmp = (uint32_t) (tmp >> 1U); 03596 } 03597 return nbChannels; 03598 } 03599 03600 /** 03601 * @brief This function allows to get the channel number from channel instance. 03602 * @param Instance DFSDM channel instance. 03603 * @retval Channel number. 03604 */ 03605 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) 03606 { 03607 uint32_t channel = 0xFFU; 03608 03609 /* Get channel from instance */ 03610 #if defined(DFSDM2_Channel0) 03611 if((Instance == DFSDM1_Channel0) || (Instance == DFSDM2_Channel0)) 03612 { 03613 channel = 0U; 03614 } 03615 else if((Instance == DFSDM1_Channel1) || (Instance == DFSDM2_Channel1)) 03616 { 03617 channel = 1U; 03618 } 03619 else if((Instance == DFSDM1_Channel2) || (Instance == DFSDM2_Channel2)) 03620 { 03621 channel = 2U; 03622 } 03623 else if((Instance == DFSDM1_Channel3) || (Instance == DFSDM2_Channel3)) 03624 { 03625 channel = 3U; 03626 } 03627 else if(Instance == DFSDM2_Channel4) 03628 { 03629 channel = 4U; 03630 } 03631 else if(Instance == DFSDM2_Channel5) 03632 { 03633 channel = 5U; 03634 } 03635 else if(Instance == DFSDM2_Channel6) 03636 { 03637 channel = 6U; 03638 } 03639 else if(Instance == DFSDM2_Channel7) 03640 { 03641 channel = 7U; 03642 } 03643 #else 03644 if(Instance == DFSDM1_Channel0) 03645 { 03646 channel = 0U; 03647 } 03648 else if(Instance == DFSDM1_Channel1) 03649 { 03650 channel = 1U; 03651 } 03652 else if(Instance == DFSDM1_Channel2) 03653 { 03654 channel = 2U; 03655 } 03656 else if(Instance == DFSDM1_Channel3) 03657 { 03658 channel = 3U; 03659 } 03660 #endif /* defined(DFSDM2_Channel0) */ 03661 03662 return channel; 03663 } 03664 03665 /** 03666 * @brief This function allows to really start regular conversion. 03667 * @param hdfsdm_filter DFSDM filter handle. 03668 * @retval None 03669 */ 03670 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) 03671 { 03672 /* Check regular trigger */ 03673 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) 03674 { 03675 /* Software start of regular conversion */ 03676 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; 03677 } 03678 else /* synchronous trigger */ 03679 { 03680 /* Disable DFSDM filter */ 03681 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); 03682 03683 /* Set RSYNC bit in DFSDM_FLTCR1 register */ 03684 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC; 03685 03686 /* Enable DFSDM filter */ 03687 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; 03688 03689 /* If injected conversion was in progress, restart it */ 03690 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) 03691 { 03692 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) 03693 { 03694 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; 03695 } 03696 /* Update remaining injected conversions */ 03697 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ 03698 hdfsdm_filter->InjectedChannelsNbr : 1U; 03699 } 03700 } 03701 /* Update DFSDM filter state */ 03702 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ 03703 HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ; 03704 } 03705 03706 /** 03707 * @brief This function allows to really stop regular conversion. 03708 * @param hdfsdm_filter DFSDM filter handle. 03709 * @retval None 03710 */ 03711 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) 03712 { 03713 /* Disable DFSDM filter */ 03714 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); 03715 03716 /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */ 03717 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) 03718 { 03719 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); 03720 } 03721 03722 /* Enable DFSDM filter */ 03723 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; 03724 03725 /* If injected conversion was in progress, restart it */ 03726 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) 03727 { 03728 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) 03729 { 03730 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; 03731 } 03732 /* Update remaining injected conversions */ 03733 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ 03734 hdfsdm_filter->InjectedChannelsNbr : 1U; 03735 } 03736 03737 /* Update DFSDM filter state */ 03738 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ 03739 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; 03740 } 03741 03742 /** 03743 * @brief This function allows to really start injected conversion. 03744 * @param hdfsdm_filter DFSDM filter handle. 03745 * @retval None 03746 */ 03747 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) 03748 { 03749 /* Check injected trigger */ 03750 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) 03751 { 03752 /* Software start of injected conversion */ 03753 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; 03754 } 03755 else /* external or synchronous trigger */ 03756 { 03757 /* Disable DFSDM filter */ 03758 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); 03759 03760 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) 03761 { 03762 /* Set JSYNC bit in DFSDM_FLTCR1 register */ 03763 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC; 03764 } 03765 else /* external trigger */ 03766 { 03767 /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ 03768 hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge; 03769 } 03770 03771 /* Enable DFSDM filter */ 03772 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; 03773 03774 /* If regular conversion was in progress, restart it */ 03775 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ 03776 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) 03777 { 03778 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; 03779 } 03780 } 03781 /* Update DFSDM filter state */ 03782 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ 03783 HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ; 03784 } 03785 03786 /** 03787 * @brief This function allows to really stop injected conversion. 03788 * @param hdfsdm_filter DFSDM filter handle. 03789 * @retval None 03790 */ 03791 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) 03792 { 03793 /* Disable DFSDM filter */ 03794 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); 03795 03796 /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */ 03797 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) 03798 { 03799 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC); 03800 } 03801 else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) 03802 { 03803 /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ 03804 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN); 03805 } 03806 03807 /* Enable DFSDM filter */ 03808 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; 03809 03810 /* If regular conversion was in progress, restart it */ 03811 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ 03812 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) 03813 { 03814 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; 03815 } 03816 03817 /* Update remaining injected conversions */ 03818 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ 03819 hdfsdm_filter->InjectedChannelsNbr : 1U; 03820 03821 /* Update DFSDM filter state */ 03822 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ 03823 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; 03824 } 03825 /** 03826 * @} 03827 */ 03828 /* End of private functions --------------------------------------------------*/ 03829 03830 /** 03831 * @} 03832 */ 03833 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 03834 #endif /* HAL_DFSDM_MODULE_ENABLED */ 03835 /** 03836 * @} 03837 */ 03838 03839 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/