STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_cortex.c 00004 * @author MCD Application Team 00005 * @brief CORTEX HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the CORTEX: 00008 * + Initialization and de-initialization functions 00009 * + Peripheral Control functions 00010 * 00011 @verbatim 00012 ============================================================================== 00013 ##### How to use this driver ##### 00014 ============================================================================== 00015 00016 [..] 00017 *** How to configure Interrupts using CORTEX HAL driver *** 00018 =========================================================== 00019 [..] 00020 This section provides functions allowing to configure the NVIC interrupts (IRQ). 00021 The Cortex-M4 exceptions are managed by CMSIS functions. 00022 00023 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() 00024 function according to the following table. 00025 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 00026 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). 00027 (#) please refer to programming manual for details in how to configure priority. 00028 00029 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 00030 The pending IRQ priority will be managed only by the sub priority. 00031 00032 -@- IRQ priority order (sorted by highest to lowest priority): 00033 (+@) Lowest preemption priority 00034 (+@) Lowest sub priority 00035 (+@) Lowest hardware priority (IRQ number) 00036 00037 [..] 00038 *** How to configure Systick using CORTEX HAL driver *** 00039 ======================================================== 00040 [..] 00041 Setup SysTick Timer for time base. 00042 00043 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which 00044 is a CMSIS function that: 00045 (++) Configures the SysTick Reload register with value passed as function parameter. 00046 (++) Configures the SysTick IRQ priority to the lowest value 0x0F. 00047 (++) Resets the SysTick Counter register. 00048 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). 00049 (++) Enables the SysTick Interrupt. 00050 (++) Starts the SysTick Counter. 00051 00052 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro 00053 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the 00054 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined 00055 inside the stm32f4xx_hal_cortex.h file. 00056 00057 (+) You can change the SysTick IRQ priority by calling the 00058 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 00059 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. 00060 00061 (+) To adjust the SysTick time base, use the following formula: 00062 00063 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) 00064 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function 00065 (++) Reload Value should not exceed 0xFFFFFF 00066 00067 @endverbatim 00068 ****************************************************************************** 00069 * @attention 00070 * 00071 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00072 * 00073 * Redistribution and use in source and binary forms, with or without modification, 00074 * are permitted provided that the following conditions are met: 00075 * 1. Redistributions of source code must retain the above copyright notice, 00076 * this list of conditions and the following disclaimer. 00077 * 2. Redistributions in binary form must reproduce the above copyright notice, 00078 * this list of conditions and the following disclaimer in the documentation 00079 * and/or other materials provided with the distribution. 00080 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00081 * may be used to endorse or promote products derived from this software 00082 * without specific prior written permission. 00083 * 00084 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00085 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00086 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00087 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00088 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00089 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00090 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00091 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00092 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00093 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00094 * 00095 ****************************************************************************** 00096 */ 00097 00098 /* Includes ------------------------------------------------------------------*/ 00099 #include "stm32f4xx_hal.h" 00100 00101 /** @addtogroup STM32F4xx_HAL_Driver 00102 * @{ 00103 */ 00104 00105 /** @defgroup CORTEX CORTEX 00106 * @brief CORTEX HAL module driver 00107 * @{ 00108 */ 00109 00110 #ifdef HAL_CORTEX_MODULE_ENABLED 00111 00112 /* Private types -------------------------------------------------------------*/ 00113 /* Private variables ---------------------------------------------------------*/ 00114 /* Private constants ---------------------------------------------------------*/ 00115 /* Private macros ------------------------------------------------------------*/ 00116 /* Private functions ---------------------------------------------------------*/ 00117 /* Exported functions --------------------------------------------------------*/ 00118 00119 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 00120 * @{ 00121 */ 00122 00123 00124 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions 00125 * @brief Initialization and Configuration functions 00126 * 00127 @verbatim 00128 ============================================================================== 00129 ##### Initialization and de-initialization functions ##### 00130 ============================================================================== 00131 [..] 00132 This section provides the CORTEX HAL driver functions allowing to configure Interrupts 00133 Systick functionalities 00134 00135 @endverbatim 00136 * @{ 00137 */ 00138 00139 00140 /** 00141 * @brief Sets the priority grouping field (preemption priority and subpriority) 00142 * using the required unlock sequence. 00143 * @param PriorityGroup The priority grouping bits length. 00144 * This parameter can be one of the following values: 00145 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 00146 * 4 bits for subpriority 00147 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 00148 * 3 bits for subpriority 00149 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 00150 * 2 bits for subpriority 00151 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 00152 * 1 bits for subpriority 00153 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 00154 * 0 bits for subpriority 00155 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 00156 * The pending IRQ priority will be managed only by the subpriority. 00157 * @retval None 00158 */ 00159 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 00160 { 00161 /* Check the parameters */ 00162 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); 00163 00164 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ 00165 NVIC_SetPriorityGrouping(PriorityGroup); 00166 } 00167 00168 /** 00169 * @brief Sets the priority of an interrupt. 00170 * @param IRQn External interrupt number. 00171 * This parameter can be an enumerator of IRQn_Type enumeration 00172 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) 00173 * @param PreemptPriority The preemption priority for the IRQn channel. 00174 * This parameter can be a value between 0 and 15 00175 * A lower priority value indicates a higher priority 00176 * @param SubPriority the subpriority level for the IRQ channel. 00177 * This parameter can be a value between 0 and 15 00178 * A lower priority value indicates a higher priority. 00179 * @retval None 00180 */ 00181 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) 00182 { 00183 uint32_t prioritygroup = 0x00U; 00184 00185 /* Check the parameters */ 00186 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); 00187 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); 00188 00189 prioritygroup = NVIC_GetPriorityGrouping(); 00190 00191 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 00192 } 00193 00194 /** 00195 * @brief Enables a device specific interrupt in the NVIC interrupt controller. 00196 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 00197 * function should be called before. 00198 * @param IRQn External interrupt number. 00199 * This parameter can be an enumerator of IRQn_Type enumeration 00200 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) 00201 * @retval None 00202 */ 00203 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) 00204 { 00205 /* Check the parameters */ 00206 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00207 00208 /* Enable interrupt */ 00209 NVIC_EnableIRQ(IRQn); 00210 } 00211 00212 /** 00213 * @brief Disables a device specific interrupt in the NVIC interrupt controller. 00214 * @param IRQn External interrupt number. 00215 * This parameter can be an enumerator of IRQn_Type enumeration 00216 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) 00217 * @retval None 00218 */ 00219 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) 00220 { 00221 /* Check the parameters */ 00222 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00223 00224 /* Disable interrupt */ 00225 NVIC_DisableIRQ(IRQn); 00226 } 00227 00228 /** 00229 * @brief Initiates a system reset request to reset the MCU. 00230 * @retval None 00231 */ 00232 void HAL_NVIC_SystemReset(void) 00233 { 00234 /* System Reset */ 00235 NVIC_SystemReset(); 00236 } 00237 00238 /** 00239 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. 00240 * Counter is in free running mode to generate periodic interrupts. 00241 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. 00242 * @retval status: - 0 Function succeeded. 00243 * - 1 Function failed. 00244 */ 00245 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) 00246 { 00247 return SysTick_Config(TicksNumb); 00248 } 00249 /** 00250 * @} 00251 */ 00252 00253 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 00254 * @brief Cortex control functions 00255 * 00256 @verbatim 00257 ============================================================================== 00258 ##### Peripheral Control functions ##### 00259 ============================================================================== 00260 [..] 00261 This subsection provides a set of functions allowing to control the CORTEX 00262 (NVIC, SYSTICK, MPU) functionalities. 00263 00264 00265 @endverbatim 00266 * @{ 00267 */ 00268 00269 #if (__MPU_PRESENT == 1U) 00270 /** 00271 * @brief Disables the MPU 00272 * @retval None 00273 */ 00274 void HAL_MPU_Disable(void) 00275 { 00276 /* Make sure outstanding transfers are done */ 00277 __DMB(); 00278 00279 /* Disable fault exceptions */ 00280 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 00281 00282 /* Disable the MPU and clear the control register*/ 00283 MPU->CTRL = 0U; 00284 } 00285 00286 /** 00287 * @brief Enable the MPU. 00288 * @param MPU_Control Specifies the control mode of the MPU during hard fault, 00289 * NMI, FAULTMASK and privileged access to the default memory 00290 * This parameter can be one of the following values: 00291 * @arg MPU_HFNMI_PRIVDEF_NONE 00292 * @arg MPU_HARDFAULT_NMI 00293 * @arg MPU_PRIVILEGED_DEFAULT 00294 * @arg MPU_HFNMI_PRIVDEF 00295 * @retval None 00296 */ 00297 void HAL_MPU_Enable(uint32_t MPU_Control) 00298 { 00299 /* Enable the MPU */ 00300 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 00301 00302 /* Enable fault exceptions */ 00303 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 00304 00305 /* Ensure MPU setting take effects */ 00306 __DSB(); 00307 __ISB(); 00308 } 00309 00310 /** 00311 * @brief Initializes and configures the Region and the memory to be protected. 00312 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains 00313 * the initialization and configuration information. 00314 * @retval None 00315 */ 00316 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) 00317 { 00318 /* Check the parameters */ 00319 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); 00320 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); 00321 00322 /* Set the Region number */ 00323 MPU->RNR = MPU_Init->Number; 00324 00325 if ((MPU_Init->Enable) != RESET) 00326 { 00327 /* Check the parameters */ 00328 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); 00329 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); 00330 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); 00331 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); 00332 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); 00333 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); 00334 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); 00335 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); 00336 00337 MPU->RBAR = MPU_Init->BaseAddress; 00338 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 00339 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 00340 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 00341 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 00342 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 00343 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 00344 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 00345 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 00346 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 00347 } 00348 else 00349 { 00350 MPU->RBAR = 0x00U; 00351 MPU->RASR = 0x00U; 00352 } 00353 } 00354 #endif /* __MPU_PRESENT */ 00355 00356 /** 00357 * @brief Gets the priority grouping field from the NVIC Interrupt Controller. 00358 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) 00359 */ 00360 uint32_t HAL_NVIC_GetPriorityGrouping(void) 00361 { 00362 /* Get the PRIGROUP[10:8] field value */ 00363 return NVIC_GetPriorityGrouping(); 00364 } 00365 00366 /** 00367 * @brief Gets the priority of an interrupt. 00368 * @param IRQn External interrupt number. 00369 * This parameter can be an enumerator of IRQn_Type enumeration 00370 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) 00371 * @param PriorityGroup the priority grouping bits length. 00372 * This parameter can be one of the following values: 00373 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 00374 * 4 bits for subpriority 00375 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 00376 * 3 bits for subpriority 00377 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 00378 * 2 bits for subpriority 00379 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 00380 * 1 bits for subpriority 00381 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 00382 * 0 bits for subpriority 00383 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). 00384 * @param pSubPriority Pointer on the Subpriority value (starting from 0). 00385 * @retval None 00386 */ 00387 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) 00388 { 00389 /* Check the parameters */ 00390 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); 00391 /* Get priority for Cortex-M system or device specific interrupts */ 00392 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); 00393 } 00394 00395 /** 00396 * @brief Sets Pending bit of an external interrupt. 00397 * @param IRQn External interrupt number 00398 * This parameter can be an enumerator of IRQn_Type enumeration 00399 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) 00400 * @retval None 00401 */ 00402 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) 00403 { 00404 /* Check the parameters */ 00405 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00406 00407 /* Set interrupt pending */ 00408 NVIC_SetPendingIRQ(IRQn); 00409 } 00410 00411 /** 00412 * @brief Gets Pending Interrupt (reads the pending register in the NVIC 00413 * and returns the pending bit for the specified interrupt). 00414 * @param IRQn External interrupt number. 00415 * This parameter can be an enumerator of IRQn_Type enumeration 00416 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) 00417 * @retval status: - 0 Interrupt status is not pending. 00418 * - 1 Interrupt status is pending. 00419 */ 00420 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) 00421 { 00422 /* Check the parameters */ 00423 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00424 00425 /* Return 1 if pending else 0 */ 00426 return NVIC_GetPendingIRQ(IRQn); 00427 } 00428 00429 /** 00430 * @brief Clears the pending bit of an external interrupt. 00431 * @param IRQn External interrupt number. 00432 * This parameter can be an enumerator of IRQn_Type enumeration 00433 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) 00434 * @retval None 00435 */ 00436 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00437 { 00438 /* Check the parameters */ 00439 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00440 00441 /* Clear pending interrupt */ 00442 NVIC_ClearPendingIRQ(IRQn); 00443 } 00444 00445 /** 00446 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). 00447 * @param IRQn External interrupt number 00448 * This parameter can be an enumerator of IRQn_Type enumeration 00449 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) 00450 * @retval status: - 0 Interrupt status is not pending. 00451 * - 1 Interrupt status is pending. 00452 */ 00453 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) 00454 { 00455 /* Check the parameters */ 00456 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00457 00458 /* Return 1 if active else 0 */ 00459 return NVIC_GetActive(IRQn); 00460 } 00461 00462 /** 00463 * @brief Configures the SysTick clock source. 00464 * @param CLKSource specifies the SysTick clock source. 00465 * This parameter can be one of the following values: 00466 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. 00467 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. 00468 * @retval None 00469 */ 00470 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) 00471 { 00472 /* Check the parameters */ 00473 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); 00474 if (CLKSource == SYSTICK_CLKSOURCE_HCLK) 00475 { 00476 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; 00477 } 00478 else 00479 { 00480 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; 00481 } 00482 } 00483 00484 /** 00485 * @brief This function handles SYSTICK interrupt request. 00486 * @retval None 00487 */ 00488 void HAL_SYSTICK_IRQHandler(void) 00489 { 00490 HAL_SYSTICK_Callback(); 00491 } 00492 00493 /** 00494 * @brief SYSTICK callback. 00495 * @retval None 00496 */ 00497 __weak void HAL_SYSTICK_Callback(void) 00498 { 00499 /* NOTE : This function Should not be modified, when the callback is needed, 00500 the HAL_SYSTICK_Callback could be implemented in the user file 00501 */ 00502 } 00503 00504 /** 00505 * @} 00506 */ 00507 00508 /** 00509 * @} 00510 */ 00511 00512 #endif /* HAL_CORTEX_MODULE_ENABLED */ 00513 /** 00514 * @} 00515 */ 00516 00517 /** 00518 * @} 00519 */ 00520 00521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/