STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file containing functions prototypes of ADC HAL library. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_ADC_H 00038 #define __STM32F4xx_ADC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx_hal_def.h" 00046 00047 /** @addtogroup STM32F4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup ADC 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup ADC_Exported_Types ADC Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief Structure definition of ADC and regular group initialization 00062 * @note Parameters of this structure are shared within 2 scopes: 00063 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. 00064 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 00065 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 00066 * ADC state can be either: 00067 * - For all parameters: ADC disabled 00068 * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. 00069 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. 00070 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00071 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 00072 */ 00073 typedef struct 00074 { 00075 uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for 00076 all the ADCs. 00077 This parameter can be a value of @ref ADC_ClockPrescaler */ 00078 uint32_t Resolution; /*!< Configures the ADC resolution. 00079 This parameter can be a value of @ref ADC_Resolution */ 00080 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 00081 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 00082 This parameter can be a value of @ref ADC_Data_align */ 00083 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 00084 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 00085 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 00086 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 00087 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 00088 Scan direction is upward: from rank1 to rank 'n'. 00089 This parameter can be set to ENABLE or DISABLE */ 00090 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 00091 This parameter can be a value of @ref ADC_EOCSelection. 00092 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. 00093 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) 00094 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. 00095 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). 00096 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ 00097 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 00098 after the selected trigger occurred (software start or external trigger). 00099 This parameter can be set to ENABLE or DISABLE. */ 00100 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 00101 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00102 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ 00103 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 00104 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00105 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 00106 This parameter can be set to ENABLE or DISABLE. */ 00107 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 00108 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 00109 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 00110 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 00111 If set to ADC_SOFTWARE_START, external triggers are disabled. 00112 If set to external trigger source, triggering is on event rising edge by default. 00113 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ 00114 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 00115 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 00116 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 00117 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 00118 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 00119 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 00120 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 00121 This parameter can be set to ENABLE or DISABLE. */ 00122 }ADC_InitTypeDef; 00123 00124 00125 00126 /** 00127 * @brief Structure definition of ADC channel for regular group 00128 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 00129 * ADC can be either disabled or enabled without conversion on going on regular group. 00130 */ 00131 typedef struct 00132 { 00133 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 00134 This parameter can be a value of @ref ADC_channels */ 00135 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 00136 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 00137 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 00138 Unit: ADC clock cycles 00139 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 00140 This parameter can be a value of @ref ADC_sampling_times 00141 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 00142 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 00143 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00144 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 00145 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 00146 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ 00147 }ADC_ChannelConfTypeDef; 00148 00149 /** 00150 * @brief ADC Configuration multi-mode structure definition 00151 */ 00152 typedef struct 00153 { 00154 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. 00155 This parameter can be a value of @ref ADC_analog_watchdog_selection */ 00156 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 00157 This parameter must be a 12-bit value. */ 00158 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 00159 This parameter must be a 12-bit value. */ 00160 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. 00161 This parameter has an effect only if watchdog mode is configured on single channel 00162 This parameter can be a value of @ref ADC_channels */ 00163 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured 00164 is interrupt mode or in polling mode. 00165 This parameter can be set to ENABLE or DISABLE */ 00166 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 00167 }ADC_AnalogWDGConfTypeDef; 00168 00169 /** 00170 * @brief HAL ADC state machine: ADC states definition (bitfields) 00171 */ 00172 /* States of ADC global scope */ 00173 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ 00174 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ 00175 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ 00176 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ 00177 00178 /* States of ADC errors */ 00179 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ 00180 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ 00181 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ 00182 00183 /* States of ADC group regular */ 00184 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 00185 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 00186 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ 00187 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */ 00188 00189 /* States of ADC group injected */ 00190 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 00191 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 00192 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ 00193 00194 /* States of ADC analog watchdogs */ 00195 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ 00196 #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */ 00197 #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */ 00198 00199 /* States of ADC multi-mode */ 00200 #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */ 00201 00202 00203 /** 00204 * @brief ADC handle Structure definition 00205 */ 00206 typedef struct 00207 { 00208 ADC_TypeDef *Instance; /*!< Register base address */ 00209 00210 ADC_InitTypeDef Init; /*!< ADC required parameters */ 00211 00212 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ 00213 00214 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 00215 00216 HAL_LockTypeDef Lock; /*!< ADC locking object */ 00217 00218 __IO uint32_t State; /*!< ADC communication state */ 00219 00220 __IO uint32_t ErrorCode; /*!< ADC Error code */ 00221 }ADC_HandleTypeDef; 00222 /** 00223 * @} 00224 */ 00225 00226 /* Exported constants --------------------------------------------------------*/ 00227 /** @defgroup ADC_Exported_Constants ADC Exported Constants 00228 * @{ 00229 */ 00230 00231 /** @defgroup ADC_Error_Code ADC Error Code 00232 * @{ 00233 */ 00234 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ 00235 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, 00236 enable/disable, erroneous state */ 00237 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ 00238 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ 00239 /** 00240 * @} 00241 */ 00242 00243 00244 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler 00245 * @{ 00246 */ 00247 #define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U 00248 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) 00249 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) 00250 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) 00251 /** 00252 * @} 00253 */ 00254 00255 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases 00256 * @{ 00257 */ 00258 #define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U 00259 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) 00260 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) 00261 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 00262 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) 00263 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 00264 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 00265 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 00266 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) 00267 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) 00268 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) 00269 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) 00270 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) 00271 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) 00272 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) 00273 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) 00274 /** 00275 * @} 00276 */ 00277 00278 /** @defgroup ADC_Resolution ADC Resolution 00279 * @{ 00280 */ 00281 #define ADC_RESOLUTION_12B 0x00000000U 00282 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) 00283 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) 00284 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) 00285 /** 00286 * @} 00287 */ 00288 00289 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular 00290 * @{ 00291 */ 00292 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U 00293 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) 00294 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) 00295 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) 00296 /** 00297 * @} 00298 */ 00299 00300 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular 00301 * @{ 00302 */ 00303 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ 00304 /* compatibility with other STM32 devices. */ 00305 #define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U 00306 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) 00307 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) 00308 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 00309 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) 00310 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 00311 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 00312 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 00313 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) 00314 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) 00315 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) 00316 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 00317 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) 00318 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 00319 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) 00320 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) 00321 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U) 00322 /** 00323 * @} 00324 */ 00325 00326 /** @defgroup ADC_Data_align ADC Data Align 00327 * @{ 00328 */ 00329 #define ADC_DATAALIGN_RIGHT 0x00000000U 00330 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 00331 /** 00332 * @} 00333 */ 00334 00335 /** @defgroup ADC_channels ADC Common Channels 00336 * @{ 00337 */ 00338 #define ADC_CHANNEL_0 0x00000000U 00339 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) 00340 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) 00341 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 00342 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) 00343 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 00344 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 00345 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 00346 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) 00347 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) 00348 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) 00349 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 00350 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) 00351 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) 00352 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) 00353 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) 00354 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) 00355 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) 00356 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) 00357 00358 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) 00359 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup ADC_sampling_times ADC Sampling Times 00365 * @{ 00366 */ 00367 #define ADC_SAMPLETIME_3CYCLES 0x00000000U 00368 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) 00369 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) 00370 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) 00371 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) 00372 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) 00373 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) 00374 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) 00375 /** 00376 * @} 00377 */ 00378 00379 /** @defgroup ADC_EOCSelection ADC EOC Selection 00380 * @{ 00381 */ 00382 #define ADC_EOC_SEQ_CONV 0x00000000U 00383 #define ADC_EOC_SINGLE_CONV 0x00000001U 00384 #define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */ 00385 /** 00386 * @} 00387 */ 00388 00389 /** @defgroup ADC_Event_type ADC Event Type 00390 * @{ 00391 */ 00392 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) 00393 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) 00394 /** 00395 * @} 00396 */ 00397 00398 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection 00399 * @{ 00400 */ 00401 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 00402 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 00403 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 00404 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) 00405 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) 00406 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 00407 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U 00408 /** 00409 * @} 00410 */ 00411 00412 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition 00413 * @{ 00414 */ 00415 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) 00416 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) 00417 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) 00418 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) 00419 /** 00420 * @} 00421 */ 00422 00423 /** @defgroup ADC_flags_definition ADC Flags Definition 00424 * @{ 00425 */ 00426 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) 00427 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) 00428 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) 00429 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) 00430 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) 00431 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) 00432 /** 00433 * @} 00434 */ 00435 00436 /** @defgroup ADC_channels_type ADC Channels Type 00437 * @{ 00438 */ 00439 #define ADC_ALL_CHANNELS 0x00000001U 00440 #define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */ 00441 #define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */ 00442 /** 00443 * @} 00444 */ 00445 00446 /** 00447 * @} 00448 */ 00449 00450 /* Exported macro ------------------------------------------------------------*/ 00451 /** @defgroup ADC_Exported_Macros ADC Exported Macros 00452 * @{ 00453 */ 00454 00455 /** @brief Reset ADC handle state 00456 * @param __HANDLE__ ADC handle 00457 * @retval None 00458 */ 00459 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 00460 00461 /** 00462 * @brief Enable the ADC peripheral. 00463 * @param __HANDLE__ ADC handle 00464 * @retval None 00465 */ 00466 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) 00467 00468 /** 00469 * @brief Disable the ADC peripheral. 00470 * @param __HANDLE__ ADC handle 00471 * @retval None 00472 */ 00473 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) 00474 00475 /** 00476 * @brief Enable the ADC end of conversion interrupt. 00477 * @param __HANDLE__ specifies the ADC Handle. 00478 * @param __INTERRUPT__ ADC Interrupt. 00479 * @retval None 00480 */ 00481 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) 00482 00483 /** 00484 * @brief Disable the ADC end of conversion interrupt. 00485 * @param __HANDLE__ specifies the ADC Handle. 00486 * @param __INTERRUPT__ ADC interrupt. 00487 * @retval None 00488 */ 00489 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) 00490 00491 /** @brief Check if the specified ADC interrupt source is enabled or disabled. 00492 * @param __HANDLE__ specifies the ADC Handle. 00493 * @param __INTERRUPT__ specifies the ADC interrupt source to check. 00494 * @retval The new state of __IT__ (TRUE or FALSE). 00495 */ 00496 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 00497 00498 /** 00499 * @brief Clear the ADC's pending flags. 00500 * @param __HANDLE__ specifies the ADC Handle. 00501 * @param __FLAG__ ADC flag. 00502 * @retval None 00503 */ 00504 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) 00505 00506 /** 00507 * @brief Get the selected ADC's flag status. 00508 * @param __HANDLE__ specifies the ADC Handle. 00509 * @param __FLAG__ ADC flag. 00510 * @retval None 00511 */ 00512 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 00513 00514 /** 00515 * @} 00516 */ 00517 00518 /* Include ADC HAL Extension module */ 00519 #include "stm32f4xx_hal_adc_ex.h" 00520 00521 /* Exported functions --------------------------------------------------------*/ 00522 /** @addtogroup ADC_Exported_Functions 00523 * @{ 00524 */ 00525 00526 /** @addtogroup ADC_Exported_Functions_Group1 00527 * @{ 00528 */ 00529 /* Initialization/de-initialization functions ***********************************/ 00530 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 00531 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 00532 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 00533 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 00534 /** 00535 * @} 00536 */ 00537 00538 /** @addtogroup ADC_Exported_Functions_Group2 00539 * @{ 00540 */ 00541 /* I/O operation functions ******************************************************/ 00542 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 00543 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 00544 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 00545 00546 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 00547 00548 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 00549 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 00550 00551 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 00552 00553 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 00554 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 00555 00556 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 00557 00558 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 00559 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 00560 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 00561 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 00562 /** 00563 * @} 00564 */ 00565 00566 /** @addtogroup ADC_Exported_Functions_Group3 00567 * @{ 00568 */ 00569 /* Peripheral Control functions *************************************************/ 00570 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 00571 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 00572 /** 00573 * @} 00574 */ 00575 00576 /** @addtogroup ADC_Exported_Functions_Group4 00577 * @{ 00578 */ 00579 /* Peripheral State functions ***************************************************/ 00580 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 00581 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 00582 /** 00583 * @} 00584 */ 00585 00586 /** 00587 * @} 00588 */ 00589 /* Private types -------------------------------------------------------------*/ 00590 /* Private variables ---------------------------------------------------------*/ 00591 /* Private constants ---------------------------------------------------------*/ 00592 /** @defgroup ADC_Private_Constants ADC Private Constants 00593 * @{ 00594 */ 00595 /* Delay for ADC stabilization time. */ 00596 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ 00597 /* Unit: us */ 00598 #define ADC_STAB_DELAY_US 3U 00599 /* Delay for temperature sensor stabilization time. */ 00600 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ 00601 /* Unit: us */ 00602 #define ADC_TEMPSENSOR_DELAY_US 10U 00603 /** 00604 * @} 00605 */ 00606 00607 /* Private macro ------------------------------------------------------------*/ 00608 00609 /** @defgroup ADC_Private_Macros ADC Private Macros 00610 * @{ 00611 */ 00612 /* Macro reserved for internal HAL driver usage, not intended to be used in 00613 code of final user */ 00614 00615 /** 00616 * @brief Verification of ADC state: enabled or disabled 00617 * @param __HANDLE__ ADC handle 00618 * @retval SET (ADC enabled) or RESET (ADC disabled) 00619 */ 00620 #define ADC_IS_ENABLE(__HANDLE__) \ 00621 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ 00622 ) ? SET : RESET) 00623 00624 /** 00625 * @brief Test if conversion trigger of regular group is software start 00626 * or external trigger. 00627 * @param __HANDLE__ ADC handle 00628 * @retval SET (software start) or RESET (external trigger) 00629 */ 00630 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 00631 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 00632 00633 /** 00634 * @brief Test if conversion trigger of injected group is software start 00635 * or external trigger. 00636 * @param __HANDLE__ ADC handle 00637 * @retval SET (software start) or RESET (external trigger) 00638 */ 00639 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 00640 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) 00641 00642 /** 00643 * @brief Simultaneously clears and sets specific bits of the handle State 00644 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 00645 * the first parameter is the ADC handle State, the second parameter is the 00646 * bit field to clear, the third and last parameter is the bit field to set. 00647 * @retval None 00648 */ 00649 #define ADC_STATE_CLR_SET MODIFY_REG 00650 00651 /** 00652 * @brief Clear ADC error code (set it to error code: "no error") 00653 * @param __HANDLE__ ADC handle 00654 * @retval None 00655 */ 00656 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 00657 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 00658 00659 00660 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 00661 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 00662 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ 00663 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8)) 00664 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 00665 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 00666 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 00667 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 00668 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 00669 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 00670 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 00671 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ 00672 ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ 00673 ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ 00674 ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ 00675 ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ 00676 ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ 00677 ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ 00678 ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ 00679 ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) 00680 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 00681 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 00682 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 00683 ((RESOLUTION) == ADC_RESOLUTION_6B)) 00684 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 00685 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 00686 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 00687 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) 00688 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ 00689 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ 00690 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ 00691 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 00692 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 00693 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ 00694 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 00695 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 00696 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 00697 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 00698 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ 00699 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ 00700 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ 00701 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ 00702 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ 00703 ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \ 00704 ((REGTRIG) == ADC_SOFTWARE_START)) 00705 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 00706 ((ALIGN) == ADC_DATAALIGN_LEFT)) 00707 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ 00708 ((TIME) == ADC_SAMPLETIME_15CYCLES) || \ 00709 ((TIME) == ADC_SAMPLETIME_28CYCLES) || \ 00710 ((TIME) == ADC_SAMPLETIME_56CYCLES) || \ 00711 ((TIME) == ADC_SAMPLETIME_84CYCLES) || \ 00712 ((TIME) == ADC_SAMPLETIME_112CYCLES) || \ 00713 ((TIME) == ADC_SAMPLETIME_144CYCLES) || \ 00714 ((TIME) == ADC_SAMPLETIME_480CYCLES)) 00715 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ 00716 ((EOCSelection) == ADC_EOC_SEQ_CONV) || \ 00717 ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) 00718 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 00719 ((EVENT) == ADC_OVR_EVENT)) 00720 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 00721 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 00722 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 00723 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 00724 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 00725 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ 00726 ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) 00727 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ 00728 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ 00729 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) 00730 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU) 00731 00732 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) 00733 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U))) 00734 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 00735 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 00736 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \ 00737 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \ 00738 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \ 00739 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU))) 00740 00741 /** 00742 * @brief Set ADC Regular channel sequence length. 00743 * @param _NbrOfConversion_ Regular channel sequence length. 00744 * @retval None 00745 */ 00746 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) 00747 00748 /** 00749 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 00750 * @param _SAMPLETIME_ Sample time parameter. 00751 * @param _CHANNELNB_ Channel number. 00752 * @retval None 00753 */ 00754 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) 00755 00756 /** 00757 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 00758 * @param _SAMPLETIME_ Sample time parameter. 00759 * @param _CHANNELNB_ Channel number. 00760 * @retval None 00761 */ 00762 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) 00763 00764 /** 00765 * @brief Set the selected regular channel rank for rank between 1 and 6. 00766 * @param _CHANNELNB_ Channel number. 00767 * @param _RANKNB_ Rank number. 00768 * @retval None 00769 */ 00770 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) 00771 00772 /** 00773 * @brief Set the selected regular channel rank for rank between 7 and 12. 00774 * @param _CHANNELNB_ Channel number. 00775 * @param _RANKNB_ Rank number. 00776 * @retval None 00777 */ 00778 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) 00779 00780 /** 00781 * @brief Set the selected regular channel rank for rank between 13 and 16. 00782 * @param _CHANNELNB_ Channel number. 00783 * @param _RANKNB_ Rank number. 00784 * @retval None 00785 */ 00786 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) 00787 00788 /** 00789 * @brief Enable ADC continuous conversion mode. 00790 * @param _CONTINUOUS_MODE_ Continuous mode. 00791 * @retval None 00792 */ 00793 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) 00794 00795 /** 00796 * @brief Configures the number of discontinuous conversions for the regular group channels. 00797 * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. 00798 * @retval None 00799 */ 00800 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) 00801 00802 /** 00803 * @brief Enable ADC scan mode. 00804 * @param _SCANCONV_MODE_ Scan conversion mode. 00805 * @retval None 00806 */ 00807 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) 00808 00809 /** 00810 * @brief Enable the ADC end of conversion selection. 00811 * @param _EOCSelection_MODE_ End of conversion selection mode. 00812 * @retval None 00813 */ 00814 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) 00815 00816 /** 00817 * @brief Enable the ADC DMA continuous request. 00818 * @param _DMAContReq_MODE_ DMA continuous request mode. 00819 * @retval None 00820 */ 00821 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) 00822 00823 /** 00824 * @brief Return resolution bits in CR1 register. 00825 * @param __HANDLE__ ADC handle 00826 * @retval None 00827 */ 00828 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) 00829 00830 /** 00831 * @} 00832 */ 00833 00834 /* Private functions ---------------------------------------------------------*/ 00835 /** @defgroup ADC_Private_Functions ADC Private Functions 00836 * @{ 00837 */ 00838 00839 /** 00840 * @} 00841 */ 00842 00843 /** 00844 * @} 00845 */ 00846 00847 /** 00848 * @} 00849 */ 00850 00851 #ifdef __cplusplus 00852 } 00853 #endif 00854 00855 #endif /*__STM32F4xx_ADC_H */ 00856 00857 00858 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/