STM32F439xx HAL User Manual: stm32f4xx_hal

Header file containing functions prototypes of ADC HAL library. More...

#include "stm32f4xx_hal_def.h"
#include "stm32f4xx_hal_adc_ex.h"

Data Structures
struct	ADC_InitTypeDef
	Structure definition of ADC and regular group initialization. More...
struct	ADC_ChannelConfTypeDef
	Structure definition of ADC channel for regular group. More...
struct	ADC_AnalogWDGConfTypeDef
	ADC Configuration multi-mode structure definition. More...
struct	ADC_HandleTypeDef
	ADC handle Structure definition. More...
Defines
#define	HAL_ADC_STATE_RESET 0x00000000U
	HAL ADC state machine: ADC states definition (bitfields)
#define	HAL_ADC_STATE_READY 0x00000001U
#define	HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U
#define	HAL_ADC_STATE_TIMEOUT 0x00000004U
#define	HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U
#define	HAL_ADC_STATE_ERROR_CONFIG 0x00000020U
#define	HAL_ADC_STATE_ERROR_DMA 0x00000040U
#define	HAL_ADC_STATE_REG_BUSY 0x00000100U
#define	HAL_ADC_STATE_REG_EOC 0x00000200U
#define	HAL_ADC_STATE_REG_OVR 0x00000400U
#define	HAL_ADC_STATE_INJ_BUSY 0x00001000U
#define	HAL_ADC_STATE_INJ_EOC 0x00002000U
#define	HAL_ADC_STATE_AWD1 0x00010000U
#define	HAL_ADC_STATE_AWD2 0x00020000U
#define	HAL_ADC_STATE_AWD3 0x00040000U
#define	HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U
#define	HAL_ADC_ERROR_NONE 0x00U
#define	HAL_ADC_ERROR_INTERNAL 0x01U
#define	HAL_ADC_ERROR_OVR 0x02U
#define	HAL_ADC_ERROR_DMA 0x04U
#define	ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
#define	ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define	ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define	ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
#define	ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
#define	ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define	ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define	ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
#define	ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
#define	ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0))
#define	ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1))
#define	ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
#define	ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
#define	ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0))
#define	ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1))
#define	ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
#define	ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2))
#define	ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0))
#define	ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1))
#define	ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
#define	ADC_RESOLUTION_12B 0x00000000U
#define	ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define	ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define	ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
#define	ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define	ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define	ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define	ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
#define	ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
#define	ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define	ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define	ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
#define	ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
#define	ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
#define	ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1))
#define	ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
#define	ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
#define	ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0))
#define	ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1))
#define	ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
#define	ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2))
#define	ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
#define	ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1))
#define	ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
#define	ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
#define	ADC_DATAALIGN_RIGHT 0x00000000U
#define	ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
#define	ADC_CHANNEL_0 0x00000000U
#define	ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define	ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define	ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
#define	ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
#define	ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0))
#define	ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1))
#define	ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
#define	ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
#define	ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0))
#define	ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1))
#define	ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
#define	ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2))
#define	ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0))
#define	ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1))
#define	ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
#define	ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
#define	ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0))
#define	ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1))
#define	ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
#define	ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
#define	ADC_SAMPLETIME_3CYCLES 0x00000000U
#define	ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define	ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define	ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 \| ADC_SMPR1_SMP10_0))
#define	ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
#define	ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_0))
#define	ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_1))
#define	ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
#define	ADC_EOC_SEQ_CONV 0x00000000U
#define	ADC_EOC_SINGLE_CONV 0x00000001U
#define	ADC_EOC_SINGLE_SEQ_CONV 0x00000002U
#define	ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define	ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
#define	ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
#define	ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
#define	ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
#define	ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define	ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define	ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
#define	ADC_ANALOGWATCHDOG_NONE 0x00000000U
#define	ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
#define	ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
#define	ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
#define	ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
#define	ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
#define	ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
#define	ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
#define	ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
#define	ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
#define	ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
#define	ADC_ALL_CHANNELS 0x00000001U
#define	ADC_REGULAR_CHANNELS 0x00000002U
#define	ADC_INJECTED_CHANNELS 0x00000003U
#define	__HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
	Reset ADC handle state.
#define	__HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 \|= ADC_CR2_ADON)
	Enable the ADC peripheral.
#define	__HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
	Disable the ADC peripheral.
#define	__HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) \|= (__INTERRUPT__))
	Enable the ADC end of conversion interrupt.
#define	__HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
	Disable the ADC end of conversion interrupt.
#define	__HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
	Check if the specified ADC interrupt source is enabled or disabled.
#define	__HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
	Clear the ADC's pending flags.
#define	__HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
	Get the selected ADC's flag status.
#define	ADC_STAB_DELAY_US 3U
#define	ADC_TEMPSENSOR_DELAY_US 10U
#define	ADC_IS_ENABLE(__HANDLE__)
	Verification of ADC state: enabled or disabled.
#define	ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
	Test if conversion trigger of regular group is software start or external trigger.
#define	ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
	Test if conversion trigger of injected group is software start or external trigger.
#define	ADC_STATE_CLR_SET MODIFY_REG
	Simultaneously clears and sets specific bits of the handle State.
#define	ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
	Clear ADC error code (set it to error code: "no error")
#define	IS_ADC_CLOCKPRESCALER(ADC_CLOCK)
#define	IS_ADC_SAMPLING_DELAY(DELAY)
#define	IS_ADC_RESOLUTION(RESOLUTION)
#define	IS_ADC_EXT_TRIG_EDGE(EDGE)
#define	IS_ADC_EXT_TRIG(REGTRIG)
#define	IS_ADC_DATA_ALIGN(ALIGN)
#define	IS_ADC_SAMPLE_TIME(TIME)
#define	IS_ADC_EOCSelection(EOCSelection)
#define	IS_ADC_EVENT_TYPE(EVENT)
#define	IS_ADC_ANALOG_WATCHDOG(WATCHDOG)
#define	IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE)
#define	IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
#define	IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
#define	IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))
#define	IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
#define	IS_ADC_RANGE(RESOLUTION, ADC_VALUE)
#define	ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
	Set ADC Regular channel sequence length.
#define	ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
	Set the ADC's sample time for channel numbers between 10 and 18.
#define	ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
	Set the ADC's sample time for channel numbers between 0 and 9.
#define	ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
	Set the selected regular channel rank for rank between 1 and 6.
#define	ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
	Set the selected regular channel rank for rank between 7 and 12.
#define	ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
	Set the selected regular channel rank for rank between 13 and 16.
#define	ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
	Enable ADC continuous conversion mode.
#define	ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos)
	Configures the number of discontinuous conversions for the regular group channels.
#define	ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
	Enable ADC scan mode.
#define	ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
	Enable the ADC end of conversion selection.
#define	ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
	Enable the ADC DMA continuous request.
#define	ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
	Return resolution bits in CR1 register.
Functions
HAL_StatusTypeDef	HAL_ADC_Init (ADC_HandleTypeDef *hadc)
	Initializes the ADCx peripheral according to the specified parameters in the ADC_InitStruct and initializes the ADC MSP.
HAL_StatusTypeDef	HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
	Deinitializes the ADCx peripheral registers to their default reset values.
__weak void	HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
	Initializes the ADC MSP.
__weak void	HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
	DeInitializes the ADC MSP.
HAL_StatusTypeDef	HAL_ADC_Start (ADC_HandleTypeDef *hadc)
	Enables ADC and starts conversion of the regular channels.
HAL_StatusTypeDef	HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
	Disables ADC and stop conversion of regular channels.
HAL_StatusTypeDef	HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
	Poll for regular conversion complete.
HAL_StatusTypeDef	HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
	Poll for conversion event.
HAL_StatusTypeDef	HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
	Enables the interrupt and starts ADC conversion of regular channels.
HAL_StatusTypeDef	HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
	Disables the interrupt and stop ADC conversion of regular channels.
void	HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
	Handles ADC interrupt request.
HAL_StatusTypeDef	HAL_ADC_Start_DMA (ADC_HandleTypeDef hadc, uint32_t pData, uint32_t Length)
	Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral.
HAL_StatusTypeDef	HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
	Disables ADC DMA (Single-ADC mode) and disables ADC peripheral.
uint32_t	HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
	Gets the converted value from data register of regular channel.
__weak void	HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
	Regular conversion complete callback in non blocking mode.
__weak void	HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
	Regular conversion half DMA transfer callback in non blocking mode.
__weak void	HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
	Analog watchdog callback in non blocking mode.
__weak void	HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
	Error ADC callback.
HAL_StatusTypeDef	HAL_ADC_ConfigChannel (ADC_HandleTypeDef hadc, ADC_ChannelConfTypeDef sConfig)
	Configures for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
HAL_StatusTypeDef	HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef hadc, ADC_AnalogWDGConfTypeDef AnalogWDGConfig)
	Configures the analog watchdog.
uint32_t	HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
	return the ADC state
uint32_t	HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
	Return the ADC error code.

Detailed Description

Header file containing functions prototypes of ADC HAL library.

Author:: MCD Application Team

Attention:

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Definition in file stm32f4xx_hal_adc.h.

Data Structures

Defines

Functions

Detailed Description

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