Enable or disable the AHB1 peripheral clock. More...

Defines
#define	__HAL_RCC_GPIOA_CLK_ENABLE()
#define	__HAL_RCC_GPIOB_CLK_ENABLE()
#define	__HAL_RCC_GPIOC_CLK_ENABLE()
#define	__HAL_RCC_GPIOH_CLK_ENABLE()
#define	__HAL_RCC_DMA1_CLK_ENABLE()
#define	__HAL_RCC_DMA2_CLK_ENABLE()
#define	__HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
#define	__HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
#define	__HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
#define	__HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
#define	__HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
#define	__HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note:: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))

Definition at line 449 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                         } while(0U)

Definition at line 430 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

Definition at line 450 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_DMA2_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 437 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))

Definition at line 445 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 402 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))

Definition at line 446 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 409 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))

Definition at line 447 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
                                        UNUSED(tmpreg); \
                                          } while(0U)

Definition at line 416 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_DISABLE ( ) (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))

Definition at line 448 of file stm32f4xx_hal_rcc.h.

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )

Value:

do { \
                                        __IO uint32_t tmpreg = 0x00U; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
                                        UNUSED(tmpreg); \
                                         } while(0U)

Definition at line 423 of file stm32f4xx_hal_rcc.h.

Defines

Detailed Description

Define Documentation